483 lines
14 KiB
C
483 lines
14 KiB
C
/****************************************************************************
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* arch/arm/src/lpc43/lpc43_cgu.c
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <errno.h>
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#include "up_arch.h"
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#include "lpc43_cgu.h"
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#include <arch/board/board.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Maximum/Threashold Frequencies *******************************************/
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#define LOW_XTAL_FREQUENCY 15000000
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#define MAX_XTAL_FREQUENCY 25000000
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#define MAX_FCLKOUT_FREQUENCY 204000000
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#define MAX_FCLKOUT_DIRECT 156000000
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#define MAX_FCCO_FRQUENCY 320000000
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/* Configuration ************************************************************/
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/* This supports configuration of CGU clocking from board-specific parameters
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* that must be provided in the board.h header file.
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*
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* That header file must provided the following values:
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*
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* BOARD_XTAL_FREQUENCY - The LPC43xx XTAL oscillator input frequency
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*/
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#ifndef BOARD_XTAL_FREQUENCY
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# error "board.h must provide the LPC43xx cystal input frequency (BOARD_XTAL_FREQUENCY)"
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#endif
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#if BOARD_XTAL_FREQUENCY >= MAX_XTAL_FREQUENCY
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# error "BOARD_XTAL_FREQUENCY exceeds the maximum value"
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#endif
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#if BOARD_FCLKOUT_FREQUENCY > MAX_FCLKOUT_FREQUENCY
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# error "BOARD_FCLKOUT_FREQUENCY exceed the maximum"
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#endif
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#if BOARD_FCCO_FREQUENCY > MAX_FCCO_FRQUENCY
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# error "BOARD_FCCO_FREQUENCY exceed the maximum"
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#endif
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/* Convert the user-friendly definitions in board.h to register bit settings */
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/* Check if we are using a RAMP */
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#undef PLL_RAMP
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#ifdef BOARD_PLL_RAMP_MSEL
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# define PLL_RAMP 1
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/* Get initial PLL values */
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# define INIT_MSEL_VALUE PLL1_CTRL_MSEL(1)
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# define INIT_NSEL_VALUE PLL1_CTRL_NSEL_DIV1
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/* Pick the initial PSEL value (integer mode) */
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# ifndef BOARD_XTAL_FREQUENCY
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# error "BOARD_XTAL_FREQUENCY is not defined in board.h"
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# endif
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# if BOARD_XTAL_FREQUENCY >= MAX_FCLKOUT_DIRECT
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# error "BOARD_XTAL_FREQUENCY value is not supported"
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# endif
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# if (2 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
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# error "Impossible value for BOARD_XTAL_FREQUENCY"
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# elif (2 * 2 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
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# define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
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# elif (2 * 4 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
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# define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
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# elif (2 * 8 * BOARD_XTAL_FREQUENCY) > MAX_FCCO_FRQUENCY
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# define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
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# else
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# define INIT_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
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# endif
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/* Select initial integer mode controls */
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# define INIT_PLL_CONTROLS \
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(PLL1_CTRL_FBSEL | INIT_PSEL_VALUE | INIT_NSEL_VALUE | INIT_MSEL_VALUE)
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/* Select a value close to a 10 millisecond delay */
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# define XTAL_DELAY \
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(10 * BOARD_XTAL_FREQUENCY + (LPC43_CCLK - 1)) / LPC43_CCLK
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/* Check the ramp-up MSEL value */
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# if (BOARD_PLL_RAMP_MSEL > 0) && (BOARD_PLL_RAMP_MSEL < 256)
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# define RAMP_MSEL_VALUE PLL1_CTRL_MSEL(BOARD_PLL_RAMP_MSEL)
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# else
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# error "Unsupported value of BOARD_PLL_RAMP_NSEL"
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# endif
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/* Check the ramp-up NSEL value */
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# ifndef BOARD_PLL_RAMP_NSEL
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# error "BOARD_PLL_RAMP_NSEL is not defined in board.h"
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# endif
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# if BOARD_PLL_RAMP_NSEL == 1
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# define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV1
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# elif BOARD_PLL_RAMP_NSEL == 2
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# define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV2
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# elif BOARD_PLL_RAMP_NSEL == 3
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# define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV3
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# elif BOARD_PLL_RAMP_NSEL == 4
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# define RAMP_NSEL_VALUE PLL1_CTRL_NSEL_DIV4
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# else
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# error "Unsupported value of BOARD_PLL_RAMP_NSEL"
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# endif
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/* Check for direct mode */
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# ifndef BOARD_RAMP_FCLKOUT
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# error "BOARD_RAMP_FCLKOUT is not defined in board.h"
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# endif
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# if BOARD_RAMP_FCLKOUT >= MAX_FCLKOUT_DIRECT
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/* Select direct mode controls */
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# define RAMP_PLL_CONTROLS \
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(PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT | RAMP_NSEL_VALUE | RAMP_MSEL_VALUE)
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# else
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/* Check the ramp-up PSEL value */
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# ifndef BOARD_PLL_RAMP_PSEL
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# error "BOARD_PLL_RAMP_PSEL is not defined in board.h"
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# endif
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# if BOARD_PLL_RAMP_PSEL == 1
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# define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
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# elif BOARD_PLL_RAMP_PSEL == 2
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# define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
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# elif BOARD_PLL_RAMP_PSEL == 4
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# define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
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# elif BOARD_PLL_RAMP_PSEL == 8
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# define RAMP_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
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# else
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# error "Unsupported value of BOARD_PLL_RAMP_PSEL"
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# endif
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# endif
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/* Select integer mode controls */
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# define RAMP_PLL_CONTROLS \
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(PLL1_CTRL_FBSEL | RAMP_PSEL_VALUE | RAMP_NSEL_VALUE | RAMP_MSEL_VALUE)
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/* Select a value close to a 10 millisecond delay */
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#endif
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/* Check the Final MSEL value */
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#ifndef BOARD_PLL_MSEL
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# error "BOARD_PLL_MSEL is not defined in board.h"
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#endif
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#if (BOARD_PLL_MSEL > 0) && (BOARD_PLL_MSEL < 256)
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# define CTRL_MSEL_VALUE PLL1_CTRL_MSEL(BOARD_PLL_MSEL)
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#else
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# error "Unsupported value of BOARD_PLL_MSEL"
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#endif
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/* Check the Final NSEL value */
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#ifndef BOARD_PLL_NSEL
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# error "BOARD_PLL_NSEL is not defined in board.h"
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#endif
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#if BOARD_PLL_NSEL == 1
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# define CTRL_NSEL_VALUE PLL1_CTRL_NSEL_DIV1
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#elif BOARD_PLL_NSEL == 2
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# define CTRL_NSEL_VALUE PLL1_CTRL_NSEL_DIV2
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#elif BOARD_PLL_NSEL == 3
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# define CTRL_NSEL_VALUE PLL1_CTRL_NSEL_DIV3
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#elif BOARD_PLL_NSEL == 4
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# define CTRL_NSEL_VALUE PLL1_CTRL_NSEL_DIV4
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#else
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# error "Unsupported value of BOARD_PLL_NSEL"
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#endif
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/* Check for direct mode */
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#ifndef BOARD_FCLKOUT_FREQUENCY
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# error "BOARD_FCLKOUT_FREQUENCY is not defined in board.h"
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#endif
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#if BOARD_FCLKOUT_FREQUENCY >= MAX_FCLKOUT_DIRECT
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/* Select direct mode controls */
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# define PLL_CONTROLS \
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(PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT | CTRL_NSEL_VALUE | CTRL_MSEL_VALUE)
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# else
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/* Check the Final PSEL value */
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# ifndef BOARD_PLL_PSEL
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# error "BOARD_PLL_PSEL is not defined in board.h"
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# endif
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# if BOARD_PLL_PSEL == 1
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# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV1
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# elif BOARD_PLL_PSEL == 2
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# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV2
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# elif BOARD_PLL_PSEL == 4
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# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV4
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# elif BOARD_PLL_PSEL == 8
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# define CTRL_PSEL_VALUE PLL1_CTRL_PSEL_DIV8
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# else
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# error "Unsupported value of BOARD_PLL_PSEL"
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# endif
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/* Select integer mode controls */
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# define PLL_CONTROLS \
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(PLL1_CTRL_FBSEL | CTRL_PSEL_VALUE | CTRL_NSEL_VALUE | CTRL_MSEL_VALUE)
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc43_xtalconfig
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*
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* Description:
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* Configure the cystal input to PLL1 using the settings provided in
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* the board.h file.
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*
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****************************************************************************/
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static inline void lpc43_xtalconfig(void)
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{
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/* Configure the crystal input to PLL1 */
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uint32_t regval;
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/* Set/clear the HF bit in the crystal oscillator control register.
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* - The bit must be cleared if low-frequency oscillators (<=15MHz)
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* - The HF bit must be set for high-frequency osciallators (>20MHz)
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* - For oscillators in the range 15-20 MHz, the HF setting does not matter.
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*/
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regval = getreg32(LPC43_XTAL_OSC_CTRL);
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#if BOARD_XTAL_FREQUENCY <= LOW_XTAL_FREQUENCY
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regval &= ~XTAL_OSC_CTRL_HF;
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#else
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regval |= XTAL_OSC_CTRL_HF;
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#endif
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putreg32(regval, LPC43_XTAL_OSC_CTRL);
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/* Enable the crystal oscillator by taking it out of power down mode */
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regval &= ~XTAL_OSC_CTRL_ENABLE;
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putreg32(regval, LPC43_XTAL_OSC_CTRL);
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/* Delay for stable clock input */
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up_mdelay(20);
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/* Select the crystal oscillator as the input to PLL1 */
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regval = getreg32(LPC43_PLL1_CTRL);
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regval &= ~PLL1_CTRL_CLKSEL_MASK;
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regval |= PLL1_CLKSEL_XTAL | PLL1_CTRL_AUTOBLOCK;
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putreg32(regval, LPC43_PLL1_CTRL);
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}
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/****************************************************************************
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* Name: lpc43_pll1config
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*
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* Description:
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* Configure PLL1 dividers and multipliers per the settings in the board.h
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* file to generate the desired Fclkcout and Fcco frequencies.
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*
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****************************************************************************/
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static inline void lpc43_pll1config(uint32_t ctrlvalue)
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{
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uint32_t regval;
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/* Clear PLL1 controls:
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*
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* - PLL1_CTRL_BYPASS: Input clock bypass control
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* - PLL1_CTRL_FBSEL: PLL1 feedback select
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* - PLL1_CTRL_DIRECT: PLL1 direct CCO output
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* - PLL1_CTRL_PSEL_MASK: Post-divider division ratio P (psel)
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* - PLL1_CTRL_NSEL_MASK: Pre-divider division ratio N (nsel)
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* - PLL1_CTRL_MSEL_MASK: Feedback-divider division ratio M (msel)
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*/
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regval = getreg32(LPC43_PLL1_CTRL);
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regval &= ~(PLL1_CTRL_BYPASS | PLL1_CTRL_FBSEL | PLL1_CTRL_DIRECT |
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PLL1_CTRL_PSEL_MASK | PLL1_CTRL_NSEL_MASK |
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PLL1_CTRL_MSEL_MASK);
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/* Set selected PLL1 controls:
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*
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* - PLL1_CTRL_FBSEL: Set in both integer and direct modes
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* - PLL1_CTRL_DIRECT: Set in direct mode
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* - PLL1_CTRL_PSEL: Set to the value from board.h (integer mode only)
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* - PLL1_CTRL_NSEL: Set to the value from board.h
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* - PLL1_CTRL_MSEL: Set to the value from board.h
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*/
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regval |= ctrlvalue;
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putreg32(regval, LPC43_PLL1_CTRL);
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}
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/****************************************************************************
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* Name: lpc43_pll1enable
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*
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* Description:
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* Take PLL1 out of power-down mode and wait until it is locked onto the
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* input clock.
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*
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****************************************************************************/
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static inline void lpc43_pll1enable(void)
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{
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uint32_t regval;
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/* Take PLL1 out of power down mode. The reset state of the PD bit
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* is one, i.e., powered down.
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*/
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regval = getreg32(LPC43_PLL1_CTRL);
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regval &= ~PLL1_CTRL_PD;
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putreg32(regval, LPC43_PLL1_CTRL);
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/* When the power-down mode is terminated, PPL1 will resume its normal
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* operation and will make the lock signal high once it has regained
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* lock on the input clock
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*
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* Wait for PLL1 to report that it is locked.
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*/
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while ((getreg32(LPC43_PLL1_STAT) & PLL1_STAT_LOCK) == 0);
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}
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/****************************************************************************
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* Name: lpc43_m4clkselect
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*
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* Description:
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* Select PLL1 output as the Cortex-M4 source clock.
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*
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****************************************************************************/
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static inline void lpc43_m4clkselect(uint32_t clksel)
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{
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uint32_t regval;
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regval = getreg32(LPC43_BASE_M4_CLK);
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regval &= ~BASE_M4_CLK_CLKSEL_MASK;
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regval |= clksel;
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putreg32(regval, LPC43_BASE_M4_CLK);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc43_clockconfig
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*
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* Description:
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* Called to initialize the LPC43XX. This does whatever setup is needed
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* to put the MCU in a usable state. This includes the initialization of
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* clocking using the settings in board.h.
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*
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****************************************************************************/
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void lpc43_clockconfig(void)
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{
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/* Configure the crystal input to PLL1 */
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lpc43_xtalconfig();
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#ifndef PLL_RAMP
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/* Configure PLL1 */
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lpc43_pll1config(PLL_CONTROLS);
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/* Enable PLL1 */
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lpc43_pll1enable();
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/* Set up PLL1 output as the M4 clock */
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lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1);
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#else
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/* Drive the M4 clock from the XTAL until the PLL is configured */
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lpc43_m4clkselect(BASE_M4_CLKSEL_XTAL);
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/* Select the initial PLL1 configured (BOARD_XTAL_FREQUENCY x 1) */
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lpc43_pll1config(INIT_PLL_CONTROLS);
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/* Enable PLL1 */
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lpc43_pll1enable();
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/* Delay around 10 milliseconds */
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up_mdelay(XTAL_DELAY);
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/* Configure the intermediate, ramp-up configuration for PLL1 */
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lpc43_pll1config(RAMP_PLL_CONTROLS);
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/* Set up PLL1 output as the M4 clock */
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lpc43_m4clkselect(BASE_M4_CLKSEL_PLL1);
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/* Delay around 10 milliseconds */
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up_mdelay(XTAL_DELAY);
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/* Go to the final, full-speed PLL1 configuration */
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lpc43_pll1config(PLL_CONTROLS);
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#endif
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}
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