c39ef4420e
2.fix some files to fix compile warning 3.remove blueteeth header files, which are not used in nuttx core. 4.fix configs and add lost files 5.update defconfig, remove useless items 6.fix compile warning for nuttx phyplus 7.delete useless: ble, h4, zblue defconfig files form phyplus configure folder 8.fix file format check error on phyplus source code 9.fix phyplus kconfig param error 10.update configure file for nuttx
90 lines
2.9 KiB
C
90 lines
2.9 KiB
C
/****************************************************************************
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* arch/arm/src/phy62xx/pwrmgr.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef _HAL_PWRMGR_HD
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#define _HAL_PWRMGR_HD
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "bus_dev.h"
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#include "gpio.h"
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#define PWR_MODE_NO_SLEEP 1
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#define PWR_MODE_SLEEP 2
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#define PWR_MODE_PWROFF_NO_SLEEP 4
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/* WAKEUP FROM STANDBY MODE */
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#define WAKEUP_PIN_MAX 3
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#define HAL_PWRMGR_TASK_MAX_NUM 10
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#define RET_SRAM0 BIT(0) /* 32K, 0x1fff0000~0x1fff7fff */
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#define RET_SRAM1 BIT(1) /* 16K, 0x1fff8000~0x1fffbfff */
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#define RET_SRAM2 BIT(2) /* 16K, 0x1fffc000~0x1fffffff */
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#define DEF_CLKG_CONFIG_0 (_CLK_IOMUX | _CLK_UART0 | _CLK_GPIO | _CLK_SPIF)
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#define DEF_CLKG_CONFIG_1 (_CLK_M0_CPU | _CLK_BB |_CLK_TIMER |_CLK_BBREG \
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| _CLK_TIMER1 | _CLK_TIMER2 | _CLK_TIMER3 | \
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_CLK_TIMER4 | _CLK_COM)
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typedef struct
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{
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gpio_pin_e pin;
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gpio_polarity_e type;
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uint16_t on_time;
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} pwroff_cfg_t;
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extern uint32_t g_system_reset_cause;
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typedef void (*pwrmgr_Hdl_t)(void);
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int hal_pwrmgr_init(void);
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bool hal_pwrmgr_is_lock(MODULE_e mod);
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int hal_pwrmgr_lock(MODULE_e mod);
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int hal_pwrmgr_unlock(MODULE_e mod);
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int hal_pwrmgr_register(MODULE_e mod, pwrmgr_Hdl_t sleepHandle,
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pwrmgr_Hdl_t wakeupHandle);
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int hal_pwrmgr_unregister(MODULE_e mod);
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int hal_pwrmgr_wakeup_process(void) __attribute__((weak));
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int hal_pwrmgr_sleep_process(void) __attribute__((weak));
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int hal_pwrmgr_RAM_retention(uint32_t sram);
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int hal_pwrmgr_clk_gate_config(MODULE_e module);
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int hal_pwrmgr_RAM_retention_clr(void);
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int hal_pwrmgr_RAM_retention_set(void);
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int hal_pwrmgr_LowCurrentLdo_enable(void);
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int hal_pwrmgr_LowCurrentLdo_disable(void);
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void hal_pwrmgr_poweroff(pwroff_cfg_t *pcfg, uint8_t wakeup_pin_num);
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void hal_pwrmgr_enter_standby(pwroff_cfg_t *pcfg, uint8_t wakeup_pin_num);
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#ifdef __cplusplus
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}
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#endif
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#endif
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