Tiago Medicci Serrano 007dd34ce8 esp32s3/spiflash: Fix error to pause the other CPU during operation ... Whenever a SPI flash operation will take place, it's necessary to disable the cache and run no code from the flash. This includes pausing the other CPU (when `CONFIG_SMP=y`). This commit prevents an error to occur when the CPU core is evaluated before the task is increased to the max priority.		2024-03-29 16:14:27 +08:00
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include	comments/docs: fix typos in comments	2024-03-06 13:31:50 +08:00
src	esp32s3/spiflash: Fix error to pause the other CPU during operation	2024-03-29 16:14:27 +08:00
Kconfig	xtensa/esp32s3: Tasks use SPIRAM as stack can do SPI flash read/write/erase/map/unmap	2023-12-12 22:10:38 -08:00