007dd34ce8
Whenever a SPI flash operation will take place, it's necessary to disable the cache and run no code from the flash. This includes pausing the other CPU (when `CONFIG_SMP=y`). This commit prevents an error to occur when the CPU core is evaluated before the task is increased to the max priority. |
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.. | ||
common | ||
esp32 | ||
esp32s2 | ||
esp32s3 | ||
lx6 | ||
lx7 | ||
.gitignore | ||
Makefile |