d913639a1b
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5433 42af7a65-404d-4744-a932-0658087f49c3
223 lines
8.6 KiB
NASM
223 lines
8.6 KiB
NASM
;**************************************************************************
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; arch/z80/src/z180/z180_vectcommon.asm
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;
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; Copyright (C) 2012 Gregory Nutt. All rights reserved.
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; Author: Gregory Nutt <gnutt@nuttx.org>
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; 1. Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; 2. Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; 3. Neither the name NuttX nor the names of its contributors may be
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; used to endorse or promote products derived from this software
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; without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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; POSSIBILITY OF SUCH DAMAGE.
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;
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;**************************************************************************
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.title NuttX for the Z180
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.module z180_vectcommon
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;**************************************************************************
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; Constants
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;**************************************************************************
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; Register save area layout
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XCPT_I == 0 ; Offset 0: Saved I w/interrupt state in carry
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XCPT_BC == 2 ; Offset 1: Saved BC register
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XCPT_DE == 4 ; Offset 2: Saved DE register
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XCPT_IX == 6 ; Offset 3: Saved IX register
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XCPT_IY == 8 ; Offset 4: Saved IY register
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XCPT_SP == 10 ; Offset 5: Offset to SP at time of interrupt
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XCPT_HL == 12 ; Offset 6: Saved HL register
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XCPT_AF == 14 ; Offset 7: Saved AF register
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XCPT_PC == 16 ; Offset 8: Offset to PC at time of interrupt
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;**************************************************************************
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; Global symbols used
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;**************************************************************************
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.globl _up_doirq ; Interrupt decoding logic
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;**************************************************************************
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; Vector Handlers
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;**************************************************************************
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.area _CODE
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_up_int1:: ; Vector offset 0: External /INT1
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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push af ; Offset 7: AF (retaining flags)
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ld a, #9 ; 9 = Z180_INT1
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jr _up_vectcommon ; Remaining RST handling is common
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_up_int2:: ; Vector offset 2: External /INT2
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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push af ; Offset 7: AF (retaining flags)
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ld a, #10 ; 10 = Z180_INT2
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jr _up_vectcommon ; Remaining RST handling is common
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_up_prt0:: ; Vector offset 4: PRT channel 0
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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push af ; Offset 7: AF (retaining flags)
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ld a, #11 ; 11 = Z180_PRT0
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jr _up_vectcommon ; Remaining RST handling is common
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_up_prt1:: ; Vector offset 6: PRT channel 1
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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push af ; Offset 7: AF (retaining flags)
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ld a, #12 ; 12 = Z180_PRT1
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jr _up_vectcommon ; Remaining RST handling is common
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_up_dma0:: ; Vector offset 8: DMA channel 0
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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push af ; Offset 7: AF (retaining flags)
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ld a, #13 ; 13 = Z180_DMA0
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jr _up_vectcommon ; Remaining RST handling is common
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_up_dma1:: ; Vector offset 8: DMA channel 1
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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push af ; Offset 7: AF (retaining flags)
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ld a, #14 ; 14 = Z180_DMA1
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jr _up_vectcommon ; Remaining RST handling is common
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_up_csio:: ; Vector offset 12: Clocked serial I/O
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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push af ; Offset 7: AF (retaining flags)
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ld a, #15 ; 15 = Z180_CSIO
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jr _up_vectcommon ; Remaining RST handling is common
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_up_asci0:: ; Vector offset 14: Async channel 0
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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push af ; Offset 7: AF (retaining flags)
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ld a, #16 ; 16 = Z180_ASCI0
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jr _up_vectcommon ; Remaining RST handling is common
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_up_asci1:: ; Vector offset 16: Async channel 1
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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push af ; Offset 7: AF (retaining flags)
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ld a, #17 ; 17 = Z180_ASCI1
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jr _up_vectcommon ; Remaining RST handling is common
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_up_unused:: ; Vector offset 18: Unused
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; Save AF on the stack, set the interrupt number and jump to the
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; common reset handling logic.
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; Offset 8: Return PC is already on the stack
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push af ; Offset 7: AF (retaining flags)
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ld a, #18 ; 18 = Z180_UNUSED
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jr _up_vectcommon ; Remaining RST handling is common
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;**************************************************************************
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; Common Interrupt handler
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;**************************************************************************
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_up_vectcommon::
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; Create a register frame. SP points to top of frame + 4, pushes
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; decrement the stack pointer. Already have
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;
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; Offset 8: Return PC is already on the stack
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; Offset 7: AF (retaining flags)
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;
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; IRQ number is in A
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push hl ; Offset 6: HL
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ld hl, #(3*2) ; HL is the value of the stack pointer before
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add hl, sp ; the interrupt occurred
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push hl ; Offset 5: Stack pointer
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push iy ; Offset 4: IY
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push ix ; Offset 3: IX
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push de ; Offset 2: DE
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push bc ; Offset 1: BC
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ld b, a ; Save the reset number in B
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ld a, i ; Parity bit holds interrupt state
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push af ; Offset 0: I with interrupt state in parity
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di
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; Call the interrupt decode logic. SP points to the beginning of the reg structure
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ld hl, #0 ; Argument #2 is the beginning of the reg structure
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add hl, sp ;
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push hl ; Place argument #2 at the top of stack
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push bc ; Argument #1 is the Reset number
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inc sp ; (make byte sized)
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call _up_doirq ; Decode the IRQ
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; On return, HL points to the beginning of the reg structure to restore
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; Note that (1) the arguments pushed on the stack are not popped, and (2) the
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; original stack pointer is lost. In the normal case (no context switch),
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; HL will contain the value of the SP before the arguments were pushed.
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ld sp, hl ; Use the new stack pointer
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; Restore registers. HL points to the beginning of the reg structure to restore
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ex af, af' ; Select alternate AF
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pop af ; Offset 0: AF' = I with interrupt state in carry
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ex af, af' ; Restore original AF
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pop bc ; Offset 1: BC
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pop de ; Offset 2: DE
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pop ix ; Offset 3: IX
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pop iy ; Offset 4: IY
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exx ; Use alternate BC/DE/HL
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ld hl, #-2 ; Offset of SP to account for ret addr on stack
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pop de ; Offset 5: HL' = Stack pointer after return
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add hl, de ; HL = Stack pointer value before return
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exx ; Restore original BC/DE/HL
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pop hl ; Offset 6: HL
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pop af ; Offset 7: AF
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; Restore the stack pointer
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exx ; Use alternate BC/DE/HL
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ld sp, hl ; Set SP = saved stack pointer value before return
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exx ; Restore original BC/DE/HL
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; Restore interrupt state
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ex af, af' ; Recover interrupt state
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jp po, nointenable ; Odd parity, IFF2=0, means disabled
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ex af, af' ; Restore AF (before enabling interrupts)
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ei ; yes
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reti
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nointenable::
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ex af, af' ; Restore AF
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reti
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