b38618d0c6
arch/arm/src/lpc17xx: This commit removes support for the dedicated vector handling from the LPC17xx architectures. Only common vectors are now supported.
arch/arm/src/kinetis: This commit removes support for the dedicated vector handling from the Kinetis architectures. Only common vectors are now supported.
901 lines
23 KiB
Plaintext
901 lines
23 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_ARM
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comment "ARM Options"
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choice
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prompt "ARM MCU selection"
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default ARCH_CHIP_STM32
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config ARCH_CHIP_A1X
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bool "Allwinner A1X"
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select ARCH_CORTEXA8
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select ARCH_HAVE_FPU
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_SDRAM
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select BOOT_RUNFROMSDRAM
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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Allwinner A1X family: A10, A10S (A12), A13 (ARM Cortex-A8)
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config ARCH_CHIP_BCM2708
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bool "Broadcom BCM2708"
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select ARCH_ARM1176JZ
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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select ARCH_HAVE_TICKLESS
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config ARCH_CHIP_C5471
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bool "TMS320 C5471"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_LOWVECTORS
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select OTHER_UART_SERIALDRIVER
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---help---
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TI TMS320 C5471, A180, or DA180 (ARM7TDMI)
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config ARCH_CHIP_DM320
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bool "TMS320 DM320"
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select ARCH_ARM926EJS
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select ARCH_HAVE_LOWVECTORS
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---help---
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TI DMS320 DM320 (ARM926EJS)
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config ARCH_CHIP_EFM32
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bool "Energy Micro"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_SPI_BITORDER
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select ARMV7M_CMNVECTOR
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select ARCH_HAVE_FETCHADD
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---help---
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Energy Micro EFM32 microcontrollers (ARM Cortex-M).
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config ARCH_CHIP_IMX1
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bool "NXP/Freescale iMX.1"
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select ARCH_ARM920T
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select ARCH_HAVE_HEAP2
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select ARCH_HAVE_LOWVECTORS
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---help---
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Freescale iMX.1 architectures (ARM920T)
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config ARCH_CHIP_IMX6
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bool "NXP/Freescale iMX.6"
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select ARCH_CORTEXA9
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select ARMV7A_HAVE_L2CC_PL310
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select ARCH_HAVE_FPU
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select ARCH_HAVE_TRUSTZONE
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_SDRAM
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select BOOT_RUNFROMSDRAM
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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Freescale iMX.6 architectures (Cortex-A9)
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config ARCH_CHIP_IMXRT
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bool "NXP/Freescale iMX.RT"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_CORTEXM7
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_RAMFUNCS
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select ARCH_HAVE_TICKLESS
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_SPI_CS_CONTROL
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select ARM_HAVE_MPU_UNIFIED
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select ARMV7M_CMNVECTOR
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select ARMV7M_HAVE_STACKCHECK
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---help---
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NXP i.MX RT (ARM Cortex-M7) architectures
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config ARCH_CHIP_KINETIS
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bool "NXP/Freescale Kinetis"
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select ARCH_CORTEXM4
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_RAMFUNCS
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_I2CRESET
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select ARMV7M_CMNVECTOR
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---help---
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Freescale Kinetis Architectures (ARM Cortex-M4)
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config ARCH_CHIP_KL
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bool "NXP/Freescale Kinetis L"
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select ARCH_CORTEXM0
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select ARCH_HAVE_CMNVECTOR
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---help---
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Freescale Kinetis L Architectures (ARM Cortex-M0+)
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config ARCH_CHIP_LC823450
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bool "ON Semiconductor LC823450"
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select ARCH_CORTEXM3
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_MULTICPU
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select ARCH_HAVE_I2CRESET
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select ARCH_GLOBAL_IRQDISABLE
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---help---
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ON Semiconductor LC823450 architectures (ARM dual Cortex-M3)
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config ARCH_CHIP_LM
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bool "TI/Luminary Stellaris"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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---help---
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TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4)
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config ARCH_CHIP_LPC11XX
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bool "NXP LPC11xx"
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select ARCH_CORTEXM0
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select ARCH_HAVE_CMNVECTOR
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---help---
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NXP LPC11xx architectures (ARM Cortex-M0)
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config ARCH_CHIP_LPC17XX
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bool "NXP LPC17xx"
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select ARCH_CORTEXM3
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FETCHADD
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select ARMV7M_CMNVECTOR
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select ARMV7M_HAVE_STACKCHECK
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---help---
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NXP LPC17xx architectures (ARM Cortex-M3)
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config ARCH_CHIP_LPC214X
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bool "NXP LPC214x"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_LOWVECTORS
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---help---
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NXP LPC2145x architectures (ARM7TDMI)
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config ARCH_CHIP_LPC2378
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bool "NXP LPC2378"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_LOWVECTORS
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---help---
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NXP LPC2145x architectures (ARM7TDMI)
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config ARCH_CHIP_LPC31XX
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bool "NXP LPC31XX"
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select ARCH_ARM926EJS
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select ARCH_HAVE_LOWVECTORS
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---help---
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NPX LPC31XX architectures (ARM926EJS).
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config ARCH_CHIP_LPC43XX
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bool "NXP LPC43XX"
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select ARCH_CORTEXM4
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select ARCH_HAVE_CMNVECTOR
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select ARMV7M_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FPU
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select ARCH_HAVE_FETCHADD
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---help---
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NPX LPC43XX architectures (ARM Cortex-M4).
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config ARCH_CHIP_LPC54XX
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bool "NXP LPC54XX"
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select ARCH_CORTEXM4
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select ARCH_HAVE_CMNVECTOR
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select ARMV7M_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FPU
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select ARCH_HAVE_FETCHADD
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---help---
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NPX LPC54XX architectures (ARM Cortex-M4).
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config ARCH_CHIP_MOXART
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bool "MoxART"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_RESET
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select ARCH_HAVE_SERIAL_TERMIOS
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---help---
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MoxART family
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config ARCH_CHIP_NRF52
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bool "Nordic NRF52"
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select ARCH_CORTEXM4
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select ARCH_HAVE_CMNVECTOR
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select ARMV7M_CMNVECTOR
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#select ARCH_HAVE_MPU
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#select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FPU
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---help---
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Nordic NRF52 architectures (ARM Cortex-M4).
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config ARCH_CHIP_NUC1XX
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bool "Nuvoton NUC100/120"
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select ARCH_CORTEXM0
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select ARCH_HAVE_CMNVECTOR
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---help---
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Nuvoton NUC100/120 architectures (ARM Cortex-M0).
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config ARCH_CHIP_SAMA5
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bool "Atmel SAMA5"
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select ARCH_CORTEXA5
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select ARCH_HAVE_FPU
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_TICKLESS
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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Atmel SAMA5 (ARM Cortex-A5)
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config ARCH_CHIP_SAMD
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bool "Atmel SAMD"
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select ARCH_CORTEXM0
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select ARCH_HAVE_CMNVECTOR
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---help---
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Atmel SAMD (ARM Cortex-M0+)
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config ARCH_CHIP_SAML
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bool "Atmel SAML"
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select ARCH_CORTEXM0
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select ARCH_HAVE_CMNVECTOR
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---help---
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Atmel SAML (ARM Cortex-M0+)
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config ARCH_CHIP_SAM34
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bool "Atmel SAM3/SAM4"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_RAMFUNCS
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select ARMV7M_CMNVECTOR
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select ARMV7M_HAVE_STACKCHECK
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---help---
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Atmel SAM3 (ARM Cortex-M3) and SAM4 (ARM Cortex-M4) architectures
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config ARCH_CHIP_SAMV7
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bool "Atmel SAMV7"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_CORTEXM7
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_RAMFUNCS
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select ARCH_HAVE_TICKLESS
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_SPI_CS_CONTROL
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select ARM_HAVE_MPU_UNIFIED
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select ARMV7M_CMNVECTOR
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select ARMV7M_HAVE_STACKCHECK
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---help---
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Atmel SAMV7 (ARM Cortex-M7) architectures
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config ARCH_CHIP_STM32
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bool "STMicro STM32 F1/F2/F3/F4/L1"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_PROGMEM
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select ARCH_HAVE_SPI_BITORDER
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select ARCH_HAVE_TICKLESS
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select ARCH_HAVE_TIMEKEEPING
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select ARM_HAVE_MPU_UNIFIED
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select ARMV7M_HAVE_STACKCHECK
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---help---
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STMicro STM32 architectures (ARM Cortex-M3/4).
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config ARCH_CHIP_STM32F0
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bool "STMicro STM32 F0"
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select ARCH_CORTEXM0
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select ARCH_HAVE_CMNVECTOR
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---help---
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STMicro STM32 architectures (ARM Cortex-M0).
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config ARCH_CHIP_STM32F7
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bool "STMicro STM32 F7"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_CORTEXM7
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_SPI_BITORDER
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select ARM_HAVE_MPU_UNIFIED
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select ARMV7M_CMNVECTOR
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select ARMV7M_HAVE_STACKCHECK
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---help---
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STMicro STM32 architectures (ARM Cortex-M7).
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config ARCH_CHIP_STM32H7
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bool "STMicro STM32 H7"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_CORTEXM7
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select ARCH_HAVE_MPU
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# select ARCH_HAVE_I2CRESET
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# select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_SPI_BITORDER
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select ARM_HAVE_MPU_UNIFIED
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select ARMV7M_CMNVECTOR
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# select ARMV7M_HAVE_STACKCHECK
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depends on EXPERIMENTAL # Remove when the port is stable
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---help---
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STMicro STM32H7 architectures (ARM Cortex-M7).
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BEWARE: This is a work-in-progress and not yet ready for general
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usage. See configs/nucleo-h743zi/README.txt for the current state
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of the port.
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config ARCH_CHIP_STM32L4
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bool "STMicro STM32 L4"
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select ARCH_CORTEXM4
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_PROGMEM
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select ARCH_HAVE_SPI_BITORDER
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select ARCH_HAVE_TICKLESS
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select ARM_HAVE_MPU_UNIFIED
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select ARMV7M_CMNVECTOR
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select ARMV7M_HAVE_STACKCHECK
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---help---
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STMicro STM32 architectures (ARM Cortex-M4).
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config ARCH_CHIP_STR71X
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bool "STMicro STR71x"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_LOWVECTORS
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---help---
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STMicro STR71x architectures (ARM7TDMI).
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config ARCH_CHIP_TMS570
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bool "TI TMS570"
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select ENDIAN_BIG
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_RAMFUNCS
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select ARMV7R_MEMINIT
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select ARMV7R_HAVE_DECODEFIQ
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---help---
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TI TMS570 family
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config ARCH_CHIP_TIVA
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bool "TI Tiva"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FPU
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select ARCH_HAVE_FETCHADD
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---help---
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TI Tiva TM4C architectures (ARM Cortex-M4)
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config ARCH_CHIP_XMC4
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bool "Infineon XMC4xxx"
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select ARCH_HAVE_CMNVECTOR
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select ARCH_CORTEXM4
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_RAMFUNCS
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select ARCH_HAVE_I2CRESET
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select ARM_HAVE_MPU_UNIFIED
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select ARMV7M_CMNVECTOR
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select ARMV7M_HAVE_STACKCHECK
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---help---
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Infineon XMC4xxx(ARM Cortex-M4) architectures
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endchoice
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config ARCH_ARM7TDMI
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bool
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default n
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---help---
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The Arm7TDMI-S is an excellent workhorse processor capable of a wide
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array of applications. Traditionally used in mobile handsets, the
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processor is now broadly in many non-mobile applications.
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config ARCH_ARM920T
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bool
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default n
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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---help---
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The ARM9 processor family is built around the ARM9TDMI processor and
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incorporates the 16-bit Thumb instruction set. The ARM9 Thumb family
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includes the ARM920T and ARM922T cached processor macrocells:
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- Dual 16k caches for applications running Symbian OS, Palm OS,
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Linux and Windows CE,
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- Dual 8k caches for applications running Symbian OS, Palm OS, Linux
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and Windows CE Applications
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config ARCH_ARM926EJS
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bool
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default n
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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---help---
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Arm926EJ-S is the entry point processor capable of supporting full
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Operating Systems including Linux, WindowsCE, and Symbian.
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The ARM9E processor family enables single processor solutions for
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microcontroller, DSP and Java applications. The ARM9E family of
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products are DSP-enhanced 32-bit RISC processors, for applications
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requiring a mix of DSP and microcontroller performance. The family
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includes the ARM926EJ-S, ARM946E-S, ARM966E-S, and ARM968E-S
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processor macrocells. They include signal processing extensions to
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enhance 16-bit fixed point performance using a single-cycle 32 x 16
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multiply-accumulate (MAC) unit, and implement the 16-bit Thumb
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instruction set. The ARM926EJ-S processor also includes ARM Jazelle
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technology which enables the direct execution of Java bytecodes in
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hardware.
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config ARCH_ARM1136J
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bool
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default n
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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---help---
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Arm1136J(F)-S is very similar to Arm926EJ-S, but includes an
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extended pipeline, basic SIMD (Single Instruction Multiple Data)
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instructions, and improved frequency and performance.
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config ARCH_ARM1156T2
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bool
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default n
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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---help---
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Arm1156T2(F)-S is the highest-performance processor in the real-time
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Classic Arm family.
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config ARCH_ARM1176JZ
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bool
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default n
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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---help---
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Arm1176JZ(F)-S is the highest-performance single-core processor in
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the Classic Arm family. It also introduced TrustZone technology to
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enable secure execution outside of the reach of malicious code.
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config ARCH_CORTEXM0
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bool
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default n
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_RESET
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config ARCH_CORTEXM23
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bool
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default n
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|
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config ARCH_CORTEXM3
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bool
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default n
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_RAMVECTORS
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select ARCH_HAVE_HIPRI_INTERRUPT
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select ARCH_HAVE_RESET
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config ARCH_CORTEXM33
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bool
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default n
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|
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config ARCH_CORTEXM4
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bool
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default n
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_RAMVECTORS
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|
select ARCH_HAVE_HIPRI_INTERRUPT
|
|
select ARCH_HAVE_RESET
|
|
|
|
config ARCH_CORTEXM7
|
|
bool
|
|
default n
|
|
select ARCH_HAVE_FPU
|
|
select ARCH_HAVE_IRQPRIO
|
|
select ARCH_HAVE_RAMVECTORS
|
|
select ARCH_HAVE_HIPRI_INTERRUPT
|
|
select ARCH_HAVE_RESET
|
|
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
|
|
|
|
config ARCH_CORTEXA5
|
|
bool
|
|
default n
|
|
select ARCH_HAVE_MMU
|
|
select ARCH_USE_MMU
|
|
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
|
|
|
|
config ARCH_CORTEXA8
|
|
bool
|
|
default n
|
|
select ARCH_HAVE_MMU
|
|
select ARCH_USE_MMU
|
|
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
|
|
|
|
config ARCH_CORTEXA9
|
|
bool
|
|
default n
|
|
select ARCH_HAVE_MMU
|
|
select ARCH_USE_MMU
|
|
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
|
|
|
|
config ARCH_CORTEXR4
|
|
bool
|
|
default n
|
|
select ARCH_HAVE_MPU
|
|
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
|
|
|
|
config ARCH_CORTEXR4F
|
|
bool
|
|
default n
|
|
select ARCH_HAVE_MPU
|
|
select ARCH_HAVE_FPU
|
|
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
|
|
|
|
config ARCH_CORTEXR5
|
|
bool
|
|
default n
|
|
select ARCH_HAVE_MPU
|
|
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
|
|
|
|
config ARCH_CORTEXR5F
|
|
bool
|
|
default n
|
|
select ARCH_HAVE_MPU
|
|
select ARCH_HAVE_FPU
|
|
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
|
|
|
|
config ARCH_CORTEXR7
|
|
bool
|
|
default n
|
|
select ARCH_HAVE_MPU
|
|
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
|
|
|
|
config ARCH_CORTEXR7F
|
|
bool
|
|
default n
|
|
select ARCH_HAVE_MPU
|
|
select ARCH_HAVE_FPU
|
|
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
|
|
|
|
config ARCH_FAMILY
|
|
string
|
|
default "arm" if ARCH_ARM7TDMI || ARCH_ARM926EJS || ARCH_ARM920T
|
|
default "armv6-m" if ARCH_CORTEXM0
|
|
default "armv7-a" if ARCH_CORTEXA5 || ARCH_CORTEXA8 || ARCH_CORTEXA9
|
|
default "armv7-m" if ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
|
|
default "armv7-r" if ARCH_CORTEXR4 || ARCH_CORTEXR4F || ARCH_CORTEXR5 || ARCH_CORTEXR5F || ARCH_CORTEX74 || ARCH_CORTEXR7F
|
|
|
|
config ARCH_CHIP
|
|
string
|
|
default "a1x" if ARCH_CHIP_A1X
|
|
default "bcm2708" if ARCH_CHIP_BCM2708
|
|
default "c5471" if ARCH_CHIP_C5471
|
|
default "dm320" if ARCH_CHIP_DM320
|
|
default "efm32" if ARCH_CHIP_EFM32
|
|
default "imx1" if ARCH_CHIP_IMX1
|
|
default "imx6" if ARCH_CHIP_IMX6
|
|
default "imxrt" if ARCH_CHIP_IMXRT
|
|
default "kinetis" if ARCH_CHIP_KINETIS
|
|
default "kl" if ARCH_CHIP_KL
|
|
default "lc823450" if ARCH_CHIP_LC823450
|
|
default "tiva" if ARCH_CHIP_LM || ARCH_CHIP_TIVA
|
|
default "lpc11xx" if ARCH_CHIP_LPC11XX
|
|
default "lpc17xx" if ARCH_CHIP_LPC17XX
|
|
default "lpc214x" if ARCH_CHIP_LPC214X
|
|
default "lpc2378" if ARCH_CHIP_LPC2378
|
|
default "lpc31xx" if ARCH_CHIP_LPC31XX
|
|
default "lpc43xx" if ARCH_CHIP_LPC43XX
|
|
default "lpc54xx" if ARCH_CHIP_LPC54XX
|
|
default "moxart" if ARCH_CHIP_MOXART
|
|
default "nrf52" if ARCH_CHIP_NRF52
|
|
default "nuc1xx" if ARCH_CHIP_NUC1XX
|
|
default "sama5" if ARCH_CHIP_SAMA5
|
|
default "samdl" if ARCH_CHIP_SAMD || ARCH_CHIP_SAML
|
|
default "sam34" if ARCH_CHIP_SAM34
|
|
default "samv7" if ARCH_CHIP_SAMV7
|
|
default "stm32" if ARCH_CHIP_STM32
|
|
default "stm32f0" if ARCH_CHIP_STM32F0
|
|
default "stm32f7" if ARCH_CHIP_STM32F7
|
|
default "stm32h7" if ARCH_CHIP_STM32H7
|
|
default "stm32l4" if ARCH_CHIP_STM32L4
|
|
default "str71x" if ARCH_CHIP_STR71X
|
|
default "tms570" if ARCH_CHIP_TMS570
|
|
default "xmc4" if ARCH_CHIP_XMC4
|
|
|
|
config ARMV7M_USEBASEPRI
|
|
bool "Use BASEPRI Register"
|
|
default n
|
|
depends on ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
|
|
---help---
|
|
Use the BASEPRI register to enable and disable interrupts. By
|
|
default, the PRIMASK register is used for this purpose. This
|
|
usually results in hardfaults when supervisor calls are made.
|
|
Though, these hardfaults are properly handled by the RTOS, the
|
|
hardfaults can confuse some debuggers. With the BASEPRI
|
|
register, these hardfaults, will be avoided. For more details see
|
|
http://www.nuttx.org/doku.php?id=wiki:nxinternal:svcall
|
|
|
|
config ARCH_HAVE_CMNVECTOR
|
|
bool
|
|
|
|
config ARMV7M_CMNVECTOR
|
|
bool "Use common ARMv7-M vectors"
|
|
default n
|
|
depends on ARCH_HAVE_CMNVECTOR
|
|
---help---
|
|
Some architectures use their own, built-in vector logic. Some use only
|
|
the common vector logic. Some can use either their own built-in vector
|
|
logic or the common vector logic. This applies only to ARMv7-M
|
|
architectures.
|
|
|
|
config ARMV7M_LAZYFPU
|
|
bool "Lazy FPU storage"
|
|
default n
|
|
depends on ARCH_HAVE_CMNVECTOR
|
|
---help---
|
|
There are two forms of the common vector logic. There are pros and
|
|
cons to each option:
|
|
|
|
1) The standard common vector logic exploits features of the ARMv7-M
|
|
architecture to save the all of floating registers on entry into
|
|
each interrupt and then to restore the floating registers when
|
|
the interrupt returns. The primary advantage to this approach is
|
|
that floating point operations are available in interrupt
|
|
handling logic. Since the volatile registers are preserved,
|
|
operations on the floating point registers by interrupt handling
|
|
logic has no ill effect. The downside is, of course, that more
|
|
stack operations are required on each interrupt to save and store
|
|
the floating point registers. Because of the some special
|
|
features of the ARMv-M, this is not as much overhead as you might
|
|
expect, but overhead nonetheless.
|
|
|
|
2) The lazy FPU common vector logic does not save or restore
|
|
floating point registers on entry and exit from the interrupt
|
|
handler. Rather, the floating point registers are not restored
|
|
until it is absolutely necessary to do so when a context switch
|
|
occurs and the interrupt handler will be returning to a different
|
|
floating point context. Since floating point registers are not
|
|
protected, floating point operations must not be performed in
|
|
interrupt handling logic. Better interrupt performance is be
|
|
expected, however.
|
|
|
|
By default, the "standard" common vector logic is build. This
|
|
option selects the alternate lazy FPU common vector logic.
|
|
|
|
config ARCH_HAVE_FPU
|
|
bool
|
|
default n
|
|
|
|
config ARCH_HAVE_DPFPU
|
|
bool
|
|
default n
|
|
|
|
config ARCH_FPU
|
|
bool "FPU support"
|
|
default y
|
|
depends on ARCH_HAVE_FPU
|
|
---help---
|
|
Build in support for the ARM Cortex-M4 Floating Point Unit (FPU).
|
|
Check your chip specifications first; not all Cortex-M4 chips
|
|
support the FPU.
|
|
|
|
config ARCH_DPFPU
|
|
bool "Double precision FPU support"
|
|
default y
|
|
depends on ARCH_FPU && ARCH_HAVE_DPFPU
|
|
---help---
|
|
Enable toolchain support for double precision (64-bit) floating
|
|
point if both the toolchain and the hardware support it.
|
|
|
|
config ARCH_HAVE_TRUSTZONE
|
|
bool
|
|
default n
|
|
---help---
|
|
Automatically selected to indicate that the ARM CPU supports
|
|
TrustZone.
|
|
|
|
choice
|
|
prompt "TrustZone Configuration"
|
|
default ARCH_TRUSTZONE_SECURE
|
|
depends on ARCH_HAVE_TRUSTZONE
|
|
|
|
config ARCH_TRUSTZONE_SECURE
|
|
bool "All CPUs operate secure state"
|
|
|
|
config ARCH_TRUSTZONE_NONSECURE
|
|
bool "All CPUs operate non-secure state"
|
|
depends on EXPERIMENTAL
|
|
|
|
config ARCH_TRUSTZONE_BOTH
|
|
bool "CPUs operate in both secure and non-secure states"
|
|
depends on EXPERIMENTAL
|
|
|
|
endchoice # TrustZone Configuration
|
|
|
|
config ARM_HAVE_MPU_UNIFIED
|
|
bool
|
|
default n
|
|
---help---
|
|
Automatically selected to indicate that the CPU supports a
|
|
unified MPU for both instruction and data addresses.
|
|
|
|
config ARM_MPU
|
|
bool "MPU support"
|
|
default n
|
|
depends on ARCH_HAVE_MPU
|
|
select ARCH_USE_MPU
|
|
---help---
|
|
Build in support for the ARM Cortex-M3/4/7 Memory Protection Unit (MPU).
|
|
Check your chip specifications first; not all Cortex-M3/4/7 chips
|
|
support the MPU.
|
|
|
|
config ARM_MPU_NREGIONS
|
|
int "Number of MPU regions"
|
|
default 16 if ARCH_CORTEXM7
|
|
default 8 if !ARCH_CORTEXM7
|
|
depends on ARM_MPU
|
|
---help---
|
|
This is the number of protection regions supported by the MPU.
|
|
|
|
config ARCH_HAVE_LOWVECTORS
|
|
bool
|
|
|
|
config ARCH_LOWVECTORS
|
|
bool "Vectors in low memory"
|
|
default n
|
|
depends on ARCH_HAVE_LOWVECTORS
|
|
---help---
|
|
Support ARM vectors in low memory.
|
|
|
|
config ARCH_ROMPGTABLE
|
|
bool "ROM page table"
|
|
default n
|
|
depends on ARCH_USE_MMU
|
|
---help---
|
|
Support a fixed memory mapping use a (read-only) page table in ROM/FLASH.
|
|
|
|
config DEBUG_HARDFAULT
|
|
bool "Verbose Hard-Fault Debug"
|
|
default n
|
|
depends on DEBUG_FEATURES && (ARCH_CORTEXM0 || ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7)
|
|
---help---
|
|
Enables verbose debug output when a hard fault is occurs. This verbose
|
|
output is sometimes helpful when debugging difficult hard fault problems,
|
|
but may be more than you typcially want to see.
|
|
|
|
if ARCH_CORTEXM0
|
|
source arch/arm/src/armv6-m/Kconfig
|
|
endif
|
|
if ARCH_CORTEXA5 || ARCH_CORTEXA8 || ARCH_CORTEXA9
|
|
source arch/arm/src/armv7-a/Kconfig
|
|
endif
|
|
if ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
|
|
source arch/arm/src/armv7-m/Kconfig
|
|
endif
|
|
if ARCH_CORTEXR4 || ARCH_CORTEXR4F || ARCH_CORTEXR5 || ARCH_CORTEXR5F || ARCH_CORTEX74 || ARCH_CORTEXR7F
|
|
source arch/arm/src/armv7-r/Kconfig
|
|
endif
|
|
if ARCH_ARM7TDMI || ARCH_ARM920T || ARCH_ARM926EJS || ARCH_ARM1136J || ARCH_ARM1156T2 || ARCH_ARM1176JZ
|
|
source arch/arm/src/arm/Kconfig
|
|
endif
|
|
if ARCH_CHIP_A1X
|
|
source arch/arm/src/a1x/Kconfig
|
|
endif
|
|
if ARCH_CHIP_BCM2708
|
|
source arch/arm/src/bcm2708/Kconfig
|
|
endif
|
|
if ARCH_CHIP_C5471
|
|
source arch/arm/src/c5471/Kconfig
|
|
endif
|
|
if ARCH_CHIP_DM320
|
|
source arch/arm/src/dm320/Kconfig
|
|
endif
|
|
if ARCH_CHIP_EFM32
|
|
source arch/arm/src/efm32/Kconfig
|
|
endif
|
|
if ARCH_CHIP_IMX1
|
|
source arch/arm/src/imx1/Kconfig
|
|
endif
|
|
if ARCH_CHIP_IMX6
|
|
source arch/arm/src/imx6/Kconfig
|
|
endif
|
|
if ARCH_CHIP_IMXRT
|
|
source arch/arm/src/imxrt/Kconfig
|
|
endif
|
|
if ARCH_CHIP_KINETIS
|
|
source arch/arm/src/kinetis/Kconfig
|
|
endif
|
|
if ARCH_CHIP_KL
|
|
source arch/arm/src/kl/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LC823450
|
|
source arch/arm/src/lc823450/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LM || ARCH_CHIP_TIVA
|
|
source arch/arm/src/tiva/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC11XX
|
|
source arch/arm/src/lpc11xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC17XX
|
|
source arch/arm/src/lpc17xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC214X
|
|
source arch/arm/src/lpc214x/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC2378
|
|
source arch/arm/src/lpc2378/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC31XX
|
|
source arch/arm/src/lpc31xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC43XX
|
|
source arch/arm/src/lpc43xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC54XX
|
|
source arch/arm/src/lpc54xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_MOXART
|
|
source arch/arm/src/moxart/Kconfig
|
|
endif
|
|
if ARCH_CHIP_NRF52
|
|
source arch/arm/src/nrf52/Kconfig
|
|
endif
|
|
if ARCH_CHIP_NUC1XX
|
|
source arch/arm/src/nuc1xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_SAMA5
|
|
source arch/arm/src/sama5/Kconfig
|
|
endif
|
|
if ARCH_CHIP_SAMD || ARCH_CHIP_SAML
|
|
source arch/arm/src/samdl/Kconfig
|
|
endif
|
|
if ARCH_CHIP_SAM34
|
|
source arch/arm/src/sam34/Kconfig
|
|
endif
|
|
if ARCH_CHIP_SAMV7
|
|
source arch/arm/src/samv7/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STM32
|
|
source arch/arm/src/stm32/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STM32F0
|
|
source arch/arm/src/stm32f0/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STM32F7
|
|
source arch/arm/src/stm32f7/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STM32H7
|
|
source arch/arm/src/stm32h7/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STM32L4
|
|
source arch/arm/src/stm32l4/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STR71X
|
|
source arch/arm/src/str71x/Kconfig
|
|
endif
|
|
if ARCH_CHIP_TMS570
|
|
source arch/arm/src/tms570/Kconfig
|
|
endif
|
|
if ARCH_CHIP_XMC4
|
|
source arch/arm/src/xmc4/Kconfig
|
|
endif
|
|
|
|
endif # ARCH_ARM
|