57127b9429
This implements initial support for kernel build (address environments, page allocator) for RISC-V. This is done a bit differently compared to the ARMV7 implementation: - Support implemented for Sv39 MMU, however the implementation should be extensible for other MMU types also. - Instead of preserving and moving the L1 references around, a canonical approach is used instead, where the page table base address register is switched upon context switch. - To preserve a bit of memory, only a single L1/L2 table is supported, this gives access to 1GiB of virtual memory for each process, which should be more than enough. Some things worth noting: - Assumes page pool is mapped with vaddr=paddr mappings - The CONFIG_ARCH_XXXX_VBASE and CONFIG_ARCH_XXXX_NPAGES values are ignored, with the exception of CONFIG_ARCH_DATA_VBASE which is used for ARCH_DATA_RESERVE - ARCH_DATA_RESERVE is placed at the beginning of the userspace task's address environment
185 lines
5.0 KiB
C
185 lines
5.0 KiB
C
/****************************************************************************
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* arch/risc-v/include/arch.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/arch.h
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*/
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#ifndef __ARCH_RISCV_INCLUDE_ARCH_H
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#define __ARCH_RISCV_INCLUDE_ARCH_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stddef.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef __ASSEMBLY__
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# define __STR(s) s
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#else
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# define __STR(s) #s
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#endif
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#define __XSTR(s) __STR(s)
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#if defined(CONFIG_ARCH_QPFPU)
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# define FLOAD __STR(flq)
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# define FSTORE __STR(fsq)
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#elif defined(CONFIG_ARCH_DPFPU)
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# define FLOAD __STR(fld)
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# define FSTORE __STR(fsd)
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#else
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# define FLOAD __STR(flw)
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# define FSTORE __STR(fsw)
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#endif
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#ifdef CONFIG_ARCH_RV32
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# define REGLOAD __STR(lw)
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# define REGSTORE __STR(sw)
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#else
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# define REGLOAD __STR(ld)
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# define REGSTORE __STR(sd)
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#endif
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/* RISC-V requires a 16-byte stack alignment. */
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#define STACK_ALIGNMENT 16
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#define STACK_FRAME_SIZE __XSTR(STACK_ALIGNMENT)
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/* Provide the maximum amount of page table levels per MMU type */
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#ifdef CONFIG_ARCH_MMU_TYPE_SV39
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# define ARCH_PGT_MAX_LEVELS (3)
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#endif
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/* Amount of static page tables allocated for an address environment */
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#ifdef CONFIG_ARCH_ADDRENV
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# define ARCH_SPGTS (ARCH_PGT_MAX_LEVELS - 1)
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Name: up_getsp
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****************************************************************************/
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static inline uintptr_t up_getsp(void)
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{
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register uintptr_t sp;
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__asm__
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(
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"\tadd %0, x0, x2\n"
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: "=r"(sp)
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);
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return sp;
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}
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifdef CONFIG_ARCH_ADDRENV
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#ifndef __ASSEMBLY__
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/* A task group must have its L1 table in memory always, and the rest can
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* be dynamically committed to memory (and even swapped).
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*
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* In this implementation every level tables besides the final level N are
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* kept in memory always, while the level N tables are dynamically allocated.
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*
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* The implications ? They depend on the MMU type.
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*
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* For Sv39 this means that:
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* - A task can not have more than 1GB of memory allocated. This should be
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* plenty enough...
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* - The minimum amount of memory needed for page tables per task is 12K,
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* which gives access to 2MB of memory. This is plenty for many tasks.
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*/
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struct group_addrenv_s
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{
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/* Pointers to MAX_LEVELS-1 tables here, one of each are allocated for the
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* task when it is created.
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*/
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uintptr_t spgtables[ARCH_SPGTS];
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/* For convenience store the text base here */
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uintptr_t textvbase;
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/* For convenience store the data base here */
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uintptr_t datavbase;
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/* For convenience store the heap base and initial size here */
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uintptr_t heapvbase;
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size_t heapsize;
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/* For convenience store the satp value here */
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uintptr_t satp;
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};
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typedef struct group_addrenv_s group_addrenv_t;
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/* If an address environment needs to be saved, saving the satp register
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* will suffice. The register width is architecture dependent
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*/
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typedef uintptr_t save_addrenv_t;
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_ARCH_ADDRENV */
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ARCH_RISCV_INCLUDE_ARCH_H */
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