366 lines
15 KiB
C
366 lines
15 KiB
C
/****************************************************************************
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* boards/arm/kinetis/twr-k60n512/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_KINETIS_TWR_K60N512_INCLUDE_BOARD_H
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#define __BOARDS_ARM_KINETIS_TWR_K60N512_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The K60 tower board uses a 50MHz external clock */
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#define BOARD_EXTCLOCK 1 /* External clock */
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#define BOARD_EXTAL_FREQ 50000000 /* 50MHz Oscillator */
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#define BOARD_XTAL32_FREQ 32768 /* 32KHz RTC Oscillator */
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/* PLL Configuration. Either the external clock or crystal frequency is used
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* to select the PRDIV value.
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* Only reference clock frequencies are supported that will produce a 2MHz
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* reference clock to the PLL.
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*
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* PLL Input frequency: PLLIN = REFCLK/PRDIV = 50MHz/25 = 2MHz
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* PLL Output frequency: PLLOUT = PLLIN*VDIV = 2Mhz*48 = 96MHz
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* MCG Frequency: PLLOUT = 96MHz
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*/
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#define BOARD_PRDIV 25 /* PLL External Reference Divider */
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#define BOARD_VDIV 48 /* PLL VCO Divider (frequency multiplier) */
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#define BOARD_PLLIN_FREQ (BOARD_EXTAL_FREQ / BOARD_PRDIV)
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#define BOARD_PLLOUT_FREQ (BOARD_PLLIN_FREQ * BOARD_VDIV)
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#define BOARD_MCG_FREQ BOARD_PLLOUT_FREQ
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/* SIM CLKDIV1 dividers */
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#define BOARD_OUTDIV1 1 /* Core = MCG, 96MHz */
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#define BOARD_OUTDIV2 2 /* Bus = MCG/2, 48MHz */
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#define BOARD_OUTDIV3 2 /* FlexBus = MCG/2, 48MHz */
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#define BOARD_OUTDIV4 4 /* Flash clock = MCG/4, 24MHz */
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#define BOARD_CORECLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV1)
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#define BOARD_BUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV2)
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#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3)
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#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4)
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/* SDHC clocking ************************************************************/
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/* SDCLK configurations corresponding to various modes of operation.
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* Formula is:
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*
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* SDCLK frequency = (base clock) / (prescaler * divisor)
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*
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* The SDHC module is always configure configured so that the core clock is
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* the base clock.
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*/
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/* Identification mode: 400KHz = 96MHz / ( 16 * 15) */
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#define BOARD_SDHC_IDMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16
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#define BOARD_SDHC_IDMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15)
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/* MMC normal mode: 16MHz = 96MHz / (2 * 3) */
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#define BOARD_SDHC_MMCMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
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#define BOARD_SDHC_MMCMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
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/* SD normal mode (1-bit): 16MHz = 96MHz / (2 * 3) */
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#define BOARD_SDHC_SD1MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
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#define BOARD_SDHC_SD1MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
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/* SD normal mode (4-bit): 24MHz = 96MHz / (2 * 2) (with DMA)
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* SD normal mode (4-bit): 16MHz = 96MHz / (2 * 3) (no DMA)
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*/
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#ifdef CONFIG_SDIO_DMA
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# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
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# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(2)
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#else
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/* # define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 */
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/* # define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3) */
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# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16
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# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15)
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#endif
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/* LED definitions **********************************************************/
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/* The TWR-K60N512 has four LEDs:
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*
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* 1. E1 / Orange LED PTA11
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* 2. E2 / Yellow LED PTA28
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* 3. E3 / Green LED PTA29
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* 4 E4 / Blue LED PTA10
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*
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* The 4 LEDs are encoded as follows:
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*/
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#define LED_STARTED 0 /* LED1 */
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#define LED_HEAPALLOCATE 1 /* LED2 */
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#define LED_IRQSENABLED 2 /* LED1 + LED2 */
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#define LED_STACKCREATED 3 /* LED3 */
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#define LED_INIRQ 4 /* LED1 + LED3 */
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#define LED_SIGNAL 5 /* LED2 + LED3 */
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#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */
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#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */
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/* Button definitions *******************************************************/
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/* The TWR-K60N512 has user buttons (plus a reset button):
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*
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* 1. SW1 (IRQ0) PTA19
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* 2. SW2 (IRQ1) PTE26
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*/
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#define BUTTON_SW1 0
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#define BUTTON_SW2 1
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#define BUTTON_SW1_BIT (1 << BUTTON_SW1)
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#define BUTTON_SW2_BIT (1 << BUTTON_SW2)
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/* Alternative pin resolution ***********************************************/
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/* If there are alternative configurations for various pins in the
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* kinetis_k60pinmux.h header file, those alternative pins will be labeled
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* with a suffix like _1, _2, etc. The logic in this file must select the
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* correct pin configuration for the board by defining a pin configuration
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* (with no suffix) that maps to the correct alternative.
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*/
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/* On-Board Connections
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* -------------------- ------------------------- -------- ------------------
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* FEATURE CONNECTION PORT/PIN PIN FUNCTION
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* -------------------- ------------------------- -------- ------------------
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* OSJTAG USB-to-serial OSJTAG Bridge RX Data PTE9 UART5_RX
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* Bridge OSJTAG Bridge TX Data PTE8 UART5_TX
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* SD Card Slot SD Clock PTE2 SDHC0_DCLK
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* SD Command PTE3 SDHC0_CMD
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* SD Data0 PTE1 SDHC0_D0
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* SD Data1 PTE0 SDHC0_D1
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* SD Data2 PTE5 SDHC0_D2
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* SD Data3 PTE4 SDHC0_D3
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* SD Card Detect PTE28 PTE28
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* SD Write Protect PTE27 PTE27
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* Infrared Port IR Transmit PTD7 CMT_IRO
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* IR Receive PTC6 CMP0_IN0
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* Pushbuttons SW1 (IRQ0) PTA19 PTA19
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* SW2 (IRQ1) PTE26 PTE26
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* SW3 (RESET) RESET_b RESET_b
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* Touch Pads E1 / Touch PTA4 TSI0_CH5
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* E2 / Touch PTB3 TSI0_CH8
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* E3 / Touch PTB2 TSI0_CH7
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* E4 / Touch PTB16 TSI0_CH9
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* LEDs E1 / Orange LED PTA11 PTA11
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* E2 / Yellow LED PTA28 PTA28
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* E3 / Green LED PTA29 PTA29
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* E4 / Blue LED PTA10 PTA10
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* Potentiometer Potentiometer (R71) ? ADC1_DM1
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* Accelerometer I2C SDA PTD9 I2C0_SDA
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* I2C SCL PTD8 I2C0_SCL
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* IRQ PTD10 PTD10
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* Touch Pad / Segment Electrode 0 (J3 Pin 3) PTB0 TSI0_CH0
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* LCD TWRPI Socket Electrode 1 (J3 Pin 5) PTB1 TSI0_CH6
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* Electrode 2 (J3 Pin 7) PTB2 TSI0_CH7
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* Electrode 3 (J3 Pin 8) PTB3 TSI0_CH8
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* Electrode 4 (J3 Pin 9) PTC0 TSI0_CH13
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* Electrode 5 (J3 Pin 10) PTC1 TSI0_CH14
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* Electrode 6 (J3 Pin 11) PTC2 TSI0_CH15
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* Electrode 7 (J3 Pin 12) PTA4 TSI0_CH5
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* Electrode 8 (J3 Pin 13) PTB16 TSI0_CH9
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* Electrode 9 (J3 Pin 14) PTB17 TSI0_CH10
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* Electrode 10 (J3 Pin 15) PTB18 TSI0_CH11
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* Electrode 11 (J3 Pin 16) PTB19 TSI0_CH12
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* TWRPI ID0 (J3 Pin 17) ? ADC1_DP1
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* TWRPI ID1 (J3 Pin 18) ? ADC1_SE16
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*/
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#define PIN_UART5_RX PIN_UART5_RX_2
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#define PIN_UART5_TX PIN_UART5_TX_2
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#define PIN_I2C0_SDA PIN_I2C0_SDA_3
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#define PIN_I2C0_SCL PIN_I2C0_SCL_3
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/* Connections via the General Purpose Tower Plug-in (TWRPI) Socket
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* -------------------- ------------------------- -------- ------------------
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* FEATURE CONNECTION PORT/PIN PIN FUNCTION
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* -------------------- ------------------------- -------- ------------------
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* General Purpose TWRPI AN0 (J4 Pin 8) ? ADC0_DP0/ADC1_DP3
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* TWRPI Socket TWRPI AN1 (J4 Pin 9) ? ADC0_DM0/ADC1_DM3
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* TWRPI AN2 (J4 Pin 12) ? ADC1_DP0/ADC0_DP3
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* TWRPI ID0 (J4 Pin 17) ? ADC0_DP1
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* TWRPI ID1 (J4 Pin 18) ? ADC0_DM1
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* TWRPI I2C SCL (J5 Pin 3) PTD8 I2C0_SCL
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* TWRPI I2C SDA (J5 Pin 4) PTD9 I2C0_SDA
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* TWRPI SPI MISO (J5 Pin 9) PTD14 SPI2_SIN
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* TWRPI SPI MOSI (J5 Pin 10) PTD13 SPI2_SOUT
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* TWRPI SPI SS (J5 Pin 11) PTD15 SPI2_PCS0
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* TWRPI SPI CLK (J5 Pin 12) PTD12 SPI2_SCK
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* TWRPI GPIO0 (J5 Pin 15) PTD10 PTD10
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* TWRPI GPIO1 (J5 Pin 16) PTB8 PTB8
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* TWRPI GPIO2 (J5 Pin 17) PTB9 PTB9
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* TWRPI GPIO3 (J5 Pin 18) PTA19 PTA19
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* TWRPI GPIO4 (J5 Pin 19) PTE26 PTE26
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*/
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#define PIN_SPI2_SIN PIN_SPI2_SIN_2
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#define PIN_SPI2_SOUT PIN_SPI2_SOUT_2
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#define PIN_SPI2_SCK PIN_SPI2_SCK_2
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/* Connections via the Tower Primary Connector Side A
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* --- -------------------- --------------------------------
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* PIN NAME USAGE
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* --- -------------------- --------------------------------
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* A7 SCL0 PTD8
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* A8 SDA0 PTD9
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* A9 GPIO9 / CTS1 PTC19
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* A10 GPIO8 / SDHC_D2 PTE5
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* A11 GPIO7 / SD_WP_DET PTE27
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* A13 ETH_MDC PTB1
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* A14 ETH_MDIO PTB0
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* A16 ETH_RXDV PTA14
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* A19 ETH_RXD1 PTA12
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* A20 ETH_RXD0 PTA13
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* A21 SSI_MCLK PTE6
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* A22 SSI_BCLK PTE12
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* A23 SSI_FS PTE11
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* A24 SSI_RXD PTE7
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* A25 SSI_TXD PTE10
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* A27 AN3 PGA0_DP/ADC0_DP0/ADC1_DP3
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* A28 AN2 PGA0_DM/ADC0_DM0/ADC1_DM3
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* A29 AN1 PGA1_DP/ADC1_DP0/ADC0_DP3
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* A30 AN0 PGA1_DM/ADC1_DM0/ADC0_DM3
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* A33 TMR1 PTA9
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* A34 TMR0 PTA8
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* A35 GPIO6 PTB9
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* A37 PWM3 PTA6
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* A38 PWM2 PTC3
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* A39 PWM1 PTC2
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* A40 PWM0 PTC1
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* A41 RXD0 PTE25
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* A42 TXD0 PTE24
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* A43 RXD1 PTC16
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* A44 TXD1 PTC17
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* A64 CLKOUT0 PTC3
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* A66 EBI_AD14 PTC0
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* A67 EBI_AD13 PTC1
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* A68 EBI_AD12 PTC2
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* A69 EBI_AD11 PTC4
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* A70 EBI_AD10 PTC5
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* A71 EBI_AD9 PTC6
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* A71 EBI_R/W_b PTC11
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* A72 EBI_AD8 PTC7
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* A73 EBI_AD7 PTC8
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* A74 EBI_AD6 PTC9
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* A75 EBI_AD5 PTC10
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* A76 EBI_AD4 PTD2
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* A77 EBI_AD3 PTD3
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* A78 EBI_AD2 PTD4
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* A79 EBI_AD1 PTD5
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* A80 EBI_AD0 PTD6
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*/
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/* PTE 26/27 */
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#define PIN_UART3_RX PIN_UART3_RX_2
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#define PIN_UART3_TX PIN_UART3_TX_2
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/* PTE 24/25 */
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#define PIN_UART4_RX PIN_UART4_RX_2
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#define PIN_UART4_TX PIN_UART4_TX_2
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/* Connections via the Tower Primary Connector Side B
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* --- -------------------- --------------------------------
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* PIN NAME USAGE
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* --- -------------------- --------------------------------
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* B7 SDHC_CLK / SPI1_CLK PTE2
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* B9 SDHC_D3 / SPI1_CS0_b PTE4
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* B10 SDHC_CMD / SPI1_MOSI PTE1
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* B11 SDHC_D0 / SPI1_MISO PTE3
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* B13 ETH_RXER PTA5
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* B15 ETH_TXEN PTA15
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* B19 ETH_TXD1 PTA17
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* B20 ETH_TXD0 PTA16
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* B21 GPIO1 / RTS1 PTC18
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* B22 GPIO2 / SDHC_D1 PTE0
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* B23 GPIO3 PTE28
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* B24 CLKIN0 PTA18
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* B25 CLKOUT1 PTE26
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* B27 AN7 PTB7
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* B28 AN6 PTB6
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* B29 AN5 PTB5
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* B30 AN4 PTB4
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* B34 TMR2 PTD6
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* B35 GPIO4 PTB8
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* B37 PWM7 PTA2
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* B38 PWM6 PTA1
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* B39 PWM5 PTD5
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* B40 PWM4 PTA7
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* B41 CANRX0 PTE25
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* B42 CANTX0 PTE24
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* B44 SPI0_MISO PTD14
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* B45 SPI0_MOSI PTD13
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* B46 SPI0_CS0_b PTD11
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* B47 SPI0_CS1_b PTD15
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* B48 SPI0_CLK PTD12
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* B50 SCL1 PTD8
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* B51 SDA1 PTD9
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* B52 GPIO5 / SD_CARD_DET PTE28
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* B55 IRQ_H PTA24
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* B56 IRQ_G PTA24
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* B57 IRQ_F PTA25
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* B58 IRQ_E PTA25
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* B59 IRQ_D PTA26
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* B60 IRQ_C PTA26
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* B61 IRQ_B PTA27
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* B62 IRQ_A PTA27
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* B63 EBI_ALE / EBI_CS1_b PTD0
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* B64 EBI_CS0_b PTD1
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* B66 EBI_AD15 PTB18
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* B67 EBI_AD16 PTB17
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* B68 EBI_AD17 PTB16
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* B69 EBI_AD18 PTB11
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* B70 EBI_AD19 PTB10
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* B72 EBI_OE_b PTB19
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* B73 EBI_D7 PTB20
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* B74 EBI_D6 PTB21
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* B75 EBI_D5 PTB22
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* B76 EBI_D4 PTB23
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* B77 EBI_D3 PTC12
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* B78 EBI_D2 PTC13
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* B79 EBI_D1 PTC14
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* B80 EBI_D0 PTC15
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*/
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#endif /* __BOARDS_ARM_KINETIS_TWR_K60N512_INCLUDE_BOARD_H */
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