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chip
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SAMA5: Add high-speed USB register definition header file
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2013-08-28 17:50:05 -06:00 |
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chip.h
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A few more SAMA5D3 files
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2013-07-19 17:45:28 -06:00 |
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Kconfig
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SAMA5 EHCI: Correct and extend pool allocation logic; Fix data toggle values
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2013-08-28 10:03:48 -06:00 |
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Make.defs
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Add untested OHCI driver for the SAMA5; structure naming and header files for USB host initialization prototypes
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2013-08-11 17:11:32 -06:00 |
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sam_allocateheap.c
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SAMA5: Fixes a bug in the way that the heap regions were being allocated
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2013-08-27 16:43:19 -06:00 |
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sam_boot.c
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Fix all occurrences of "the the" in documentation and comments
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2013-08-27 09:40:19 -06:00 |
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sam_clockconfig.c
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SAMA5/ECHI: Debug register access, add logic to determine transfer size, fix setting of control bit in token
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2013-08-23 16:23:15 -06:00 |
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sam_clockconfig.h
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SAMA5: Add file structure to support board-specific initialization of NOR flash
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2013-07-29 07:41:53 -06:00 |
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sam_dmac.c
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SAMA5 OHCI+EHCI: Using cp15_clean instead of cp15_coherent; EHCI: Need to set alt pointer in order to handle short transfers.
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2013-08-27 13:07:21 -06:00 |
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sam_dmac.h
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SAM3,4,A5 DMA fixes; SAMA5 SPI driver now supports DMA transfers
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2013-08-09 13:12:16 -06:00 |
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sam_ehci.c
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SAMA5 EHCI: Implemented (but did not test) interrupt endpoint logic
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2013-08-28 13:07:35 -06:00 |
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sam_hsmci.c
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SAMA5: Alternatie clock configuration that yields a perfect 48MHz full speed USB clock and a CPU clock of 384MHz
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2013-08-14 15:16:04 -06:00 |
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sam_hsmci.h
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SAMA5: Add HSMCI memory card driver support
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2013-08-05 16:21:24 -06:00 |
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sam_irq.c
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SAMA5: Add PIO interrupt support. Massive name changes for consistency in PIO vs GPIO naming. SAMA5D3x-EK: Add support for SD card detection PIO interrupts
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2013-08-06 10:20:17 -06:00 |
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sam_irq.h
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SAMA5 interrupt handling logic
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2013-07-22 11:54:39 -06:00 |
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sam_lowputc.c
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SAMA5: Add PIO interrupt support. Massive name changes for consistency in PIO vs GPIO naming. SAMA5D3x-EK: Add support for SD card detection PIO interrupts
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2013-08-06 10:20:17 -06:00 |
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sam_lowputc.h
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SAMA5 interrupt handling logic
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2013-07-22 11:54:39 -06:00 |
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sam_memories.c
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SAMA5 OHCI: Fix errors in cache handling; Don't add ED to control list until port is connected
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2013-08-15 15:28:27 -06:00 |
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sam_memories.h
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SAMA5 OHCI: Use physical address and flush and/or invalidate data caches as necessary
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2013-08-14 12:23:06 -06:00 |
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sam_ohci.c
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SAMA5 OHCI+EHCI: Using cp15_clean instead of cp15_coherent; EHCI: Need to set alt pointer in order to handle short transfers.
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2013-08-27 13:07:21 -06:00 |
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sam_periphclks.h
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Add SAMA5 GPIO configuration support
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2013-07-22 20:59:47 -06:00 |
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sam_pio.c
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SAMA5: Add PIO interrupt support. Massive name changes for consistency in PIO vs GPIO naming. SAMA5D3x-EK: Add support for SD card detection PIO interrupts
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2013-08-06 10:20:17 -06:00 |
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sam_pio.h
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SAMA5: Add PIO interrupt support. Massive name changes for consistency in PIO vs GPIO naming. SAMA5D3x-EK: Add support for SD card detection PIO interrupts
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2013-08-06 10:20:17 -06:00 |
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sam_pioirq.c
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SAMA5: Add PIO interrupt support. Massive name changes for consistency in PIO vs GPIO naming. SAMA5D3x-EK: Add support for SD card detection PIO interrupts
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2013-08-06 10:20:17 -06:00 |
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sam_serial.c
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SAMA5: Major restructuring of the the OHCI driver drivers to better handle the multiple root hub ports and concureent transfers on each port.
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2013-08-13 16:48:14 -06:00 |
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sam_serial.h
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Standard configuration variables used to enable interupt controller debug; SAMA5: Correct handling of spurious interrupts
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2013-08-03 08:22:37 -06:00 |
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sam_spi.c
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SAMA5: Centralize logic for conversion between physical and virtual addresses
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2013-08-09 17:25:53 -06:00 |
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sam_spi.h
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SAMA5: Add PIO interrupt support. Massive name changes for consistency in PIO vs GPIO naming. SAMA5D3x-EK: Add support for SD card detection PIO interrupts
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2013-08-06 10:20:17 -06:00 |
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sam_timerisr.c
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Fix Cortex-A CPSR register field definition
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2013-07-30 19:05:24 -06:00 |
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sam_usbhost.h
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SAMA5: EHCI now handles low- and full-speed connections by giving them to OHCI; OHCI now uses the work queue to defer interrupt processing; If both OHCI and EHCI are enabled, EHCI is the master of the UHPHS interrupt
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2013-08-24 11:34:24 -06:00 |
