68951e8d72
* Remove multiple newlines at the end of files * Remove the whitespace from the end of lines
318 lines
19 KiB
C
318 lines
19 KiB
C
/************************************************************************************
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* arch/arm/src/stm32l4/hardware/stm32l4_uart.h
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*
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* Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_UART_H
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#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_UART_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32L4_USART_CR1_OFFSET 0x0000 /* Control register 1 */
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#define STM32L4_USART_CR2_OFFSET 0x0004 /* Control register 2 */
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#define STM32L4_USART_CR3_OFFSET 0x0008 /* Control register 3 */
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#define STM32L4_USART_BRR_OFFSET 0x000c /* Baud Rate register */
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#define STM32L4_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
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#define STM32L4_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
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#define STM32L4_USART_RQR_OFFSET 0x0018 /* Request register */
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#define STM32L4_USART_ISR_OFFSET 0x001c /* Interrupt and status register */
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#define STM32L4_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
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#define STM32L4_USART_RDR_OFFSET 0x0024 /* Receive Data register */
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#define STM32L4_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
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/* Register Addresses ***************************************************************/
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#if STM32L4_NUSART > 0
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# define STM32L4_USART1_CR1 (STM32L4_USART1_BASE+STM32L4_USART_CR1_OFFSET)
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# define STM32L4_USART1_CR2 (STM32L4_USART1_BASE+STM32L4_USART_CR2_OFFSET)
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# define STM32L4_USART1_CR3 (STM32L4_USART1_BASE+STM32L4_USART_CR3_OFFSET)
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# define STM32L4_USART1_BRR (STM32L4_USART1_BASE+STM32L4_USART_BRR_OFFSET)
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# define STM32L4_USART1_GTPR (STM32L4_USART1_BASE+STM32L4_USART_GTPR_OFFSET)
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# define STM32L4_USART1_RTOR (STM32L4_USART1_BASE+STM32L4_USART_RTOR_OFFSET)
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# define STM32L4_USART1_RQR (STM32L4_USART1_BASE+STM32L4_USART_RQR_OFFSET)
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# define STM32L4_USART1_ISR (STM32L4_USART1_BASE+STM32L4_USART_ISR_OFFSET)
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# define STM32L4_USART1_ICR (STM32L4_USART1_BASE+STM32L4_USART_ICR_OFFSET)
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# define STM32L4_USART1_RDR (STM32L4_USART1_BASE+STM32L4_USART_RDR_OFFSET)
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# define STM32L4_USART1_TDR (STM32L4_USART1_BASE+STM32L4_USART_TDR_OFFSET)
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#endif
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#if STM32L4_NUSART > 1
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# define STM32L4_USART2_CR1 (STM32L4_USART2_BASE+STM32L4_USART_CR1_OFFSET)
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# define STM32L4_USART2_CR2 (STM32L4_USART2_BASE+STM32L4_USART_CR2_OFFSET)
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# define STM32L4_USART2_CR3 (STM32L4_USART2_BASE+STM32L4_USART_CR3_OFFSET)
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# define STM32L4_USART2_BRR (STM32L4_USART2_BASE+STM32L4_USART_BRR_OFFSET)
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# define STM32L4_USART2_GTPR (STM32L4_USART2_BASE+STM32L4_USART_GTPR_OFFSET)
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# define STM32L4_USART2_RTOR (STM32L4_USART2_BASE+STM32L4_USART_RTOR_OFFSET)
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# define STM32L4_USART2_RQR (STM32L4_USART2_BASE+STM32L4_USART_RQR_OFFSET)
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# define STM32L4_USART2_ISR (STM32L4_USART2_BASE+STM32L4_USART_ISR_OFFSET)
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# define STM32L4_USART2_ICR (STM32L4_USART2_BASE+STM32L4_USART_ICR_OFFSET)
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# define STM32L4_USART2_RDR (STM32L4_USART2_BASE+STM32L4_USART_RDR_OFFSET)
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# define STM32L4_USART2_TDR (STM32L4_USART2_BASE+STM32L4_USART_TDR_OFFSET)
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#endif
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#if STM32L4_NUSART > 2
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# define STM32L4_USART3_CR1 (STM32L4_USART3_BASE+STM32L4_USART_CR1_OFFSET)
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# define STM32L4_USART3_CR2 (STM32L4_USART3_BASE+STM32L4_USART_CR2_OFFSET)
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# define STM32L4_USART3_CR3 (STM32L4_USART3_BASE+STM32L4_USART_CR3_OFFSET)
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# define STM32L4_USART3_BRR (STM32L4_USART3_BASE+STM32L4_USART_BRR_OFFSET)
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# define STM32L4_USART3_GTPR (STM32L4_USART3_BASE+STM32L4_USART_GTPR_OFFSET)
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# define STM32L4_USART3_RTOR (STM32L4_USART3_BASE+STM32L4_USART_RTOR_OFFSET)
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# define STM32L4_USART3_RQR (STM32L4_USART3_BASE+STM32L4_USART_RQR_OFFSET)
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# define STM32L4_USART3_ISR (STM32L4_USART3_BASE+STM32L4_USART_ISR_OFFSET)
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# define STM32L4_USART3_ICR (STM32L4_USART3_BASE+STM32L4_USART_ICR_OFFSET)
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# define STM32L4_USART3_RDR (STM32L4_USART3_BASE+STM32L4_USART_RDR_OFFSET)
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# define STM32L4_USART3_TDR (STM32L4_USART3_BASE+STM32L4_USART_TDR_OFFSET)
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#endif
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#if STM32L4_NUSART > 3
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# define STM32L4_UART4_CR1 (STM32L4_UART4_BASE+STM32L4_USART_CR1_OFFSET)
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# define STM32L4_UART4_CR2 (STM32L4_UART4_BASE+STM32L4_USART_CR2_OFFSET)
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# define STM32L4_UART4_CR3 (STM32L4_UART4_BASE+STM32L4_USART_CR3_OFFSET)
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# define STM32L4_UART4_BRR (STM32L4_UART4_BASE+STM32L4_USART_BRR_OFFSET)
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# define STM32L4_UART4_GTPR (STM32L4_UART4_BASE+STM32L4_USART_GTPR_OFFSET)
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# define STM32L4_UART4_RTOR (STM32L4_UART4_BASE+STM32L4_USART_RTOR_OFFSET)
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# define STM32L4_UART4_RQR (STM32L4_UART4_BASE+STM32L4_USART_RQR_OFFSET)
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# define STM32L4_UART4_ISR (STM32L4_UART4_BASE+STM32L4_USART_ISR_OFFSET)
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# define STM32L4_UART4_ICR (STM32L4_UART4_BASE+STM32L4_USART_ICR_OFFSET)
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# define STM32L4_UART4_RDR (STM32L4_UART4_BASE+STM32L4_USART_RDR_OFFSET)
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# define STM32L4_UART4_TDR (STM32L4_UART4_BASE+STM32L4_USART_TDR_OFFSET)
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#endif
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#if STM32L4_NUSART > 4
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# define STM32L4_UART5_CR1 (STM32L4_UART5_BASE+STM32L4_USART_CR1_OFFSET)
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# define STM32L4_UART5_CR2 (STM32L4_UART5_BASE+STM32L4_USART_CR2_OFFSET)
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# define STM32L4_UART5_CR3 (STM32L4_UART5_BASE+STM32L4_USART_CR3_OFFSET)
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# define STM32L4_UART5_BRR (STM32L4_UART5_BASE+STM32L4_USART_BRR_OFFSET)
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# define STM32L4_UART5_GTPR (STM32L4_UART5_BASE+STM32L4_USART_GTPR_OFFSET)
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# define STM32L4_UART5_RTOR (STM32L4_UART5_BASE+STM32L4_USART_RTOR_OFFSET)
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# define STM32L4_UART5_RQR (STM32L4_UART5_BASE+STM32L4_USART_RQR_OFFSET)
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# define STM32L4_UART5_ISR (STM32L4_UART5_BASE+STM32L4_USART_ISR_OFFSET)
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# define STM32L4_UART5_ICR (STM32L4_UART5_BASE+STM32L4_USART_ICR_OFFSET)
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# define STM32L4_UART5_RDR (STM32L4_UART5_BASE+STM32L4_USART_RDR_OFFSET)
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# define STM32L4_UART5_TDR (STM32L4_UART5_BASE+STM32L4_USART_TDR_OFFSET)
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#endif
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/* Register Bitfield Definitions ****************************************************/
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/* Control register 1 */
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#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */
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#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode */
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#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
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#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
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#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
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#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
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#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
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#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
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#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
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#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
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#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
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#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
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#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length */
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#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
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#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
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#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
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#define USART_CR1_DEDT_SHIFT (16) /* Bits 16..20 DE deactivation delay */
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#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT)
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#define USART_CR1_DEAT_SHIFT (21) /* Bits 21..25 DE activation delay */
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#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT)
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#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
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#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */
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#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length */
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#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE| \
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USART_CR1_TCIE|USART_CR1_TXEIE|USART_CR1_PEIE|USART_CR1_CMIE| \
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USART_CR1_RTOIE|USART_CR1_EOBIE)
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/* Control register 2 */
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#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-bit/4-bit Address Detection */
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#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
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#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
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#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
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#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
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#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
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#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
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#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
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#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
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# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
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# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
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# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
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# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
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#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
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#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */
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#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */
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#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */
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#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */
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#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */
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#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud rate enable */
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#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Autobaud rate mode*/
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#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT)
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#define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* 00: Start bit */
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#define USART_CR2_ABRMOD_EDGES (1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling-to-falling edge -> frame must start with 10xxxxxx */
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#define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7F */
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#define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 */
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#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */
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#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */
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#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT)
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/* Control register 3 */
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#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
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#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
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#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
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#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
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#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
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#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
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#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
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#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
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#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
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#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
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#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
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#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method Enable */
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#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
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#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA disable on Reception error */
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#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable mode */
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#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable polarity selection */
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#define USART_CR3_SCARCNT2_SHIFT (17) /* Bits 17-19: Smart card auto retry count */
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#define USART_CR3_SCARCNT2_MASK (7 << USART_CR3_SCARCNT2_SHIFT)
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#define USART_CR3_WUS_SHIFT (20) /* Bits 20-21: Wakeup from Stop mode interrupt flag selection */
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#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT)
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#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */
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#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */
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#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */
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#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */
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/* Baud Rate Register */
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#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
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#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
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#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
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#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
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/* Guard time and prescaler register */
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#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
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#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
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#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
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#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
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/* Receiver timeout register */
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/* Request Register */
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#define USART_CR1_SBRKQ (1 << 1) /* Bit 0: Send Break */
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/* Interrupt and Status register */
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#define USART_ISR_PE (1 << 0) /* Bit 0: Parity Error */
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#define USART_ISR_FE (1 << 1) /* Bit 1: Framing Error */
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#define USART_ISR_NF (1 << 2) /* Bit 2: Noise Error Flag */
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#define USART_ISR_ORE (1 << 3) /* Bit 3: OverRun Error */
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#define USART_ISR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
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#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
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#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission Complete */
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#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
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#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN Break Detection Flag */
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#define USART_ISR_CTS (1 << 9) /* Bit 9: CTS Flag */
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#define USART_ISR_RTOF (1 << 10) /* Bit 10: Receiver timeout Flag */
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#define USART_ISR_EOBF (1 << 11) /* Bit 11: End of block Flag */
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#define USART_ISR_ABRE (1 << 12) /* Bit 12: Auto baud rate Error */
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#define USART_ISR_ABRF (1 << 14) /* Bit 14: Auto baud rate Flag */
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#define USART_ISR_BUSY (1 << 15) /* Bit 15: Busy Flag */
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#define USART_ISR_CMF (1 << 16) /* Bit 16: Character match Flag */
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#define USART_ISR_SBKF (1 << 17) /* Bit 17: Send break Flag */
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#define USART_ISR_RWU (1 << 18) /* Bit 18: Receiver wakeup from Mute mode */
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#define USART_ISR_WUF (1 << 19) /* Bit 19: Wakeup from Stop mode Flag */
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#define USART_ISR_TEACK (1 << 20) /* Bit 20: Transmit enable acknowledge Flag */
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#define USART_ISR_REACK (1 << 21) /* Bit 21: Receive enable acknowledge Flag */
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/* ICR */
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#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */
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#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */
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#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected clear flag */
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#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */
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#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */
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#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete clear flag */
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#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */
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#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS clear flag */
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#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */
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#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */
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#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */
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#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */
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/* Receive Data register */
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#define USART_RDR_SHIFT (0) /* Bits 8:0: Data value */
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#define USART_RDR_MASK (0xff << USART_RDR_SHIFT)
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/* Transmit Data register */
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#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */
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#define USART_TDR_MASK (0xff << USART_TDR_SHIFT)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_UART_H */
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