784 lines
24 KiB
C
784 lines
24 KiB
C
/************************************************************************************
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* arch/arm/src/stm3l42/stm32l4_lptim.c
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*
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* Copyright (C) 2011 Uros Platise. All rights reserved.
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* Author: Uros Platise <uros.platise@isotel.eu>
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*
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* With modifications and updates by:
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*
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* Copyright (C) 2016 Motorola Mobility, LLC. All rights reserved.
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* Copyright (C) 2011-2012, 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Copyright (c) 2015 Google, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
|
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
|
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holder nor the names of its
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* may be used to endorse or promote products derived from this
|
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <errno.h>
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#include <arch/board/board.h>
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#include "stm32l4.h"
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#include "stm32l4_gpio.h"
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#include "stm32l4_lptim.h"
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#include "stm32l4_rcc.h"
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#if defined(CONFIG_STM32L4_LPTIM1) || defined(CONFIG_STM32L4_LPTIM2)
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/************************************************************************************
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* Private Types
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************************************************************************************/
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/* TIM Device Structure */
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struct stm32l4_lptim_priv_s
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{
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const struct stm32l4_lptim_ops_s *ops;
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stm32l4_lptim_mode_t mode;
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uint32_t base; /* LPTIMn base address */
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uint32_t freq; /* Clocking for the LPTIM module */
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};
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/************************************************************************************
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* Private Function Prototypes
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************************************************************************************/
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static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer);
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static inline void stm32l4_modifyreg32(FAR struct stm32l4_lptim_dev_s *dev,
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uint8_t offset, uint32_t clearbits,
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uint32_t setbits);
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static int stm32l4_lptim_enable(FAR struct stm32l4_lptim_dev_s *dev);
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static int stm32l4_lptim_disable(FAR struct stm32l4_lptim_dev_s *dev);
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static int stm32l4_lptim_reset(FAR struct stm32l4_lptim_dev_s *dev);
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static int stm32l4_lptim_get_gpioconfig(FAR struct stm32l4_lptim_dev_s *dev,
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stm32l4_lptim_channel_t channel,
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uint32_t *cfg);
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static int stm32l4_lptim_setmode(FAR struct stm32l4_lptim_dev_s *dev,
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stm32l4_lptim_mode_t mode);
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static int stm32l4_lptim_setclock(FAR struct stm32l4_lptim_dev_s *dev,
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uint32_t freq);
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static int stm32l4_lptim_setchannel(FAR struct stm32l4_lptim_dev_s *dev,
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stm32l4_lptim_channel_t channel, int enable);
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static int stm32l4_lptim_setclocksource(FAR struct stm32l4_lptim_dev_s *dev,
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stm32l4_lptim_clksrc_t clksrc);
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static int stm32l4_lptim_setpolarity(FAR struct stm32l4_lptim_dev_s *dev,
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stm32l4_lptim_clkpol_t polarity);
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static uint32_t stm32l4_lptim_getcounter(FAR struct stm32l4_lptim_dev_s *dev);
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static int stm32l4_lptim_setcountmode(FAR struct stm32l4_lptim_dev_s *dev,
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stm32l4_lptim_cntmode_t cntmode);
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static void stm32l4_lptim_setperiod(FAR struct stm32l4_lptim_dev_s *dev,
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uint32_t period);
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static uint32_t stm32l4_lptim_getperiod(FAR struct stm32l4_lptim_dev_s *dev);
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/************************************************************************************
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* Private Data
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************************************************************************************/
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static const struct stm32l4_lptim_ops_s stm32l4_lptim_ops =
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{
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.setmode = &stm32l4_lptim_setmode,
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.setclock = &stm32l4_lptim_setclock,
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.setchannel = &stm32l4_lptim_setchannel,
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.setclocksource = &stm32l4_lptim_setclocksource,
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.setpolarity = &stm32l4_lptim_setpolarity,
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.getcounter = &stm32l4_lptim_getcounter,
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.setcountmode = &stm32l4_lptim_setcountmode,
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.setperiod = &stm32l4_lptim_setperiod,
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.getperiod = &stm32l4_lptim_getperiod
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};
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#if defined(CONFIG_STM32L4_LPTIM1)
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static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv =
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{
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.ops = &stm32l4_lptim_ops,
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.mode = STM32L4_LPTIM_MODE_UNUSED,
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.base = STM32L4_LPTIM1_BASE,
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.freq = STM32L4_LPTIM1_FREQUENCY, /* Must be defined in board.h */
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};
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#endif
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#if defined(CONFIG_STM32L4_LPTIM2)
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static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv =
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{
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.ops = &stm32l4_lptim_ops,
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.mode = STM32L4_LPTIM_MODE_UNUSED,
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.base = STM32L4_LPTIM2_BASE,
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.freq = STM32L4_LPTIM2_FREQUENCY, /* Must be defined in board.h */
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};
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#endif
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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/************************************************************************************
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* Name: stm32l4_lptim_getstruct
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************************************************************************************/
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static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer)
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{
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switch (timer)
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{
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#if defined(CONFIG_STM32L4_LPTIM1)
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case 1:
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return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim1_priv;
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#endif
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#if defined(CONFIG_STM32L4_LPTIM2)
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case 2:
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return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim2_priv;
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#endif
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default:
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return NULL;
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}
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}
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/************************************************************************************
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* Name: stm32l4_modifyreg32
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************************************************************************************/
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static inline void stm32l4_modifyreg32(FAR struct stm32l4_lptim_dev_s *dev,
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uint8_t offset, uint32_t clearbits,
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uint32_t setbits)
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{
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modifyreg32(((struct stm32l4_lptim_priv_s *)dev)->base + offset,
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clearbits, setbits);
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}
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/************************************************************************************
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* Name: stm32l4_lptim_enable
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************************************************************************************/
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static int stm32l4_lptim_enable(FAR struct stm32l4_lptim_dev_s *dev)
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{
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DEBUGASSERT(dev != NULL);
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switch (((struct stm32l4_lptim_priv_s *)dev)->base)
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{
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#if defined(CONFIG_STM32L4_LPTIM1)
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case STM32L4_LPTIM1_BASE:
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modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN);
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break;
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#endif
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#if defined(CONFIG_STM32L4_LPTIM2)
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case STM32L4_LPTIM2_BASE:
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modifyreg32(STM32L4_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN);
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break;
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#endif
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default:
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return ERROR;
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}
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return OK;
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}
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/************************************************************************************
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* Name: stm32l4_lptim_disable
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************************************************************************************/
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static int stm32l4_lptim_disable(FAR struct stm32l4_lptim_dev_s *dev)
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{
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DEBUGASSERT(dev != NULL);
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switch (((struct stm32l4_lptim_priv_s *)dev)->base)
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{
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#if defined(CONFIG_STM32L4_LPTIM1)
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case STM32L4_LPTIM1_BASE:
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modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0);
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break;
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#endif
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#if defined(CONFIG_STM32L4_LPTIM2)
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case STM32L4_LPTIM2_BASE:
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modifyreg32(STM32L4_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0);
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break;
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#endif
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default:
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return ERROR;
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}
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return OK;
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}
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/************************************************************************************
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* Name: stm32l4_lptim_reset
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************************************************************************************/
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static int stm32l4_lptim_reset(FAR struct stm32l4_lptim_dev_s *dev)
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{
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DEBUGASSERT(dev != NULL);
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switch (((struct stm32l4_lptim_priv_s *)dev)->base)
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{
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#if defined(CONFIG_STM32L4_LPTIM1)
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case STM32L4_LPTIM1_BASE:
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modifyreg32(STM32L4_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST);
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modifyreg32(STM32L4_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0);
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break;
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#endif
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#if defined(CONFIG_STM32L4_LPTIM2)
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case STM32L4_LPTIM2_BASE:
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modifyreg32(STM32L4_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST);
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modifyreg32(STM32L4_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0);
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break;
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#endif
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}
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return OK;
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}
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/************************************************************************************
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* Name: stm32l4_lptim_get_gpioconfig
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************************************************************************************/
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static int stm32l4_lptim_get_gpioconfig(FAR struct stm32l4_lptim_dev_s *dev,
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stm32l4_lptim_channel_t channel,
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uint32_t *cfg)
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{
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DEBUGASSERT(dev != NULL && cfg != NULL);
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channel &= STM32L4_LPTIM_CH_MASK;
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switch (((struct stm32l4_lptim_priv_s *)dev)->base)
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{
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#if defined(CONFIG_STM32L4_LPTIM1)
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case STM32L4_LPTIM1_BASE:
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switch (channel)
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{
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# if defined(GPIO_LPTIM1_OUT_1)
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case 1:
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*cfg = GPIO_LPTIM1_OUT_1;
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break;
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# endif
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# if defined(GPIO_LPTIM1_OUT_2)
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case 2:
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*cfg = GPIO_LPTIM1_OUT_2;
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break;
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# endif
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# if defined(GPIO_LPTIM1_OUT_3)
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case 3:
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*cfg = GPIO_LPTIM1_OUT_3;
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break;
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# endif
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default:
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return ERROR;
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}
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break;
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#endif /* CONFIG_STM32L4_LPTIM1 */
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#if defined(CONFIG_STM32L4_LPTIM2)
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case STM32L4_LPTIM2_BASE:
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switch (channel)
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{
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# if defined(GPIO_LPTIM2_OUT_1)
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case 1:
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*cfg = GPIO_LPTIM2_OUT_1;
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break;
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# endif
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# if defined(GPIO_LPTIM2_OUT_2)
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case 2:
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*cfg = GPIO_LPTIM2_OUT_2;
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break;
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# endif
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# if defined(GPIO_LPTIM2_OUT_3)
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case 3:
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*cfg = GPIO_LPTIM2_OUT_3;
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break;
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# endif
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default:
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return ERROR;
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}
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break;
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#endif /* CONFIG_STM32L4_LPTIM2 */
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default:
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return ERROR;
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}
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return OK;
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}
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/************************************************************************************
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* Name: stm32l4_lptim_setmode
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************************************************************************************/
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static int stm32l4_lptim_setmode(FAR struct stm32l4_lptim_dev_s *dev,
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stm32l4_lptim_mode_t mode)
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{
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const uint32_t addr = ((struct stm32l4_lptim_priv_s *)dev)->base +
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STM32L4_LPTIM_CR_OFFSET;
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DEBUGASSERT(dev != NULL);
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/* Mode */
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switch (mode & STM32L4_LPTIM_MODE_MASK)
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{
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case STM32L4_LPTIM_MODE_DISABLED:
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modifyreg32(addr, LPTIM_CR_ENABLE, 0);
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break;
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case STM32L4_LPTIM_MODE_SINGLE:
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modifyreg32(addr, 0, LPTIM_CR_ENABLE);
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modifyreg32(addr, 0, LPTIM_CR_SNGSTRT);
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break;
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case STM32L4_LPTIM_MODE_CONTINUOUS:
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modifyreg32(addr, 0, LPTIM_CR_ENABLE);
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modifyreg32(addr, 0, LPTIM_CR_CNTSTRT);
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break;
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default:
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return ERROR;
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}
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/* Save mode */
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((struct stm32l4_lptim_priv_s *)dev)->mode = mode;
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return OK;
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}
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/************************************************************************************
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* Name: stm32l4_lptim_setclock
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************************************************************************************/
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static int stm32l4_lptim_setclock(FAR struct stm32l4_lptim_dev_s *dev,
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uint32_t freq)
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{
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FAR struct stm32l4_lptim_priv_s *priv = (FAR struct stm32l4_lptim_priv_s *)dev;
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uint32_t setbits;
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uint32_t actual;
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DEBUGASSERT(dev != NULL);
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/* Disable Timer? */
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if (freq == 0)
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{
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stm32l4_lptim_disable(dev);
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return 0;
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}
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if (freq >= priv->freq >> 0)
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{
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/* More than clock source. This is as fast as we can go */
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setbits = LPTIM_CFGR_PRESCd1;
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actual = priv->freq >> 0;
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}
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else if (freq >= priv->freq >> 1)
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{
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setbits = LPTIM_CFGR_PRESCd2;
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actual = priv->freq >> 1;
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}
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else if (freq >= priv->freq >> 2)
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{
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setbits = LPTIM_CFGR_PRESCd4;
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actual = priv->freq >> 2;
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}
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else if (freq >= priv->freq >> 3)
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{
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setbits = LPTIM_CFGR_PRESCd8;
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actual = priv->freq >> 3;
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}
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else if (freq >= priv->freq >> 4)
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{
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setbits = LPTIM_CFGR_PRESCd16;
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actual = priv->freq >> 4;
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}
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else if (freq >= priv->freq >> 5)
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{
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setbits = LPTIM_CFGR_PRESCd32;
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actual = priv->freq >> 5;
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}
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else if (freq >= priv->freq >> 6)
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{
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setbits = LPTIM_CFGR_PRESCd64;
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actual = priv->freq >> 6;
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}
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else
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{
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/* This is as slow as we can go */
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setbits = LPTIM_CFGR_PRESCd128;
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actual = priv->freq >> 7;
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}
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stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK,
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setbits);
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stm32l4_lptim_enable(dev);
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return actual;
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}
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|
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/************************************************************************************
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* Name: stm32l4_lptim_setchannel
|
|
************************************************************************************/
|
|
|
|
static int stm32l4_lptim_setchannel(FAR struct stm32l4_lptim_dev_s *dev,
|
|
stm32l4_lptim_channel_t channel, int enable)
|
|
{
|
|
int ret = OK;
|
|
uint32_t cfg = 0;
|
|
|
|
DEBUGASSERT(dev);
|
|
|
|
/* Configure GPIOs */
|
|
|
|
ret = stm32l4_lptim_get_gpioconfig(dev, channel, &cfg);
|
|
if (!ret)
|
|
{
|
|
if (enable)
|
|
{
|
|
stm32l4_configgpio(cfg);
|
|
}
|
|
else
|
|
{
|
|
stm32l4_unconfiggpio(cfg);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: stm32l4_lptim_setclocksource
|
|
************************************************************************************/
|
|
|
|
static int stm32l4_lptim_setclocksource(FAR struct stm32l4_lptim_dev_s *dev,
|
|
stm32l4_lptim_clksrc_t clksrc)
|
|
{
|
|
FAR struct stm32l4_lptim_priv_s *priv = (FAR struct stm32l4_lptim_priv_s *)dev;
|
|
|
|
DEBUGASSERT(dev != NULL);
|
|
|
|
if (clksrc == STM32L4_LPTIM_CLK_EXT)
|
|
{
|
|
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK,
|
|
LPTIM_CFGR_CKSEL_EXTCLK);
|
|
}
|
|
else
|
|
{
|
|
uint32_t ccr_mask = 0;
|
|
|
|
switch (priv->base)
|
|
{
|
|
#ifdef CONFIG_STM32L4_LPTIM1
|
|
case STM32L4_LPTIM1_BASE:
|
|
ccr_mask = RCC_CCIPR_LPTIM1SEL_MASK;
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_STM32L4_LPTIM2
|
|
case STM32L4_LPTIM2_BASE:
|
|
ccr_mask = RCC_CCIPR_LPTIM2SEL_MASK;
|
|
break;
|
|
#endif
|
|
}
|
|
|
|
uint32_t ccr_bits = 0;
|
|
|
|
switch (clksrc)
|
|
{
|
|
case STM32L4_LPTIM_CLK_PCLK:
|
|
switch (priv->base)
|
|
{
|
|
#ifdef CONFIG_STM32L4_LPTIM1
|
|
case STM32L4_LPTIM1_BASE:
|
|
ccr_bits = RCC_CCIPR_LPTIM1SEL_PCLK;
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_STM32L4_LPTIM2
|
|
case STM32L4_LPTIM2_BASE:
|
|
ccr_bits = RCC_CCIPR_LPTIM2SEL_PCLK;
|
|
break;
|
|
#endif
|
|
}
|
|
break;
|
|
case STM32L4_LPTIM_CLK_HSI:
|
|
switch (priv->base)
|
|
{
|
|
#ifdef CONFIG_STM32L4_LPTIM1
|
|
case STM32L4_LPTIM1_BASE:
|
|
ccr_bits = RCC_CCIPR_LPTIM1SEL_HSI;
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_STM32L4_LPTIM2
|
|
case STM32L4_LPTIM2_BASE:
|
|
ccr_bits = RCC_CCIPR_LPTIM2SEL_HSI;
|
|
break;
|
|
#endif
|
|
}
|
|
break;
|
|
case STM32L4_LPTIM_CLK_LSI:
|
|
switch (priv->base)
|
|
{
|
|
#ifdef CONFIG_STM32L4_LPTIM1
|
|
case STM32L4_LPTIM1_BASE:
|
|
ccr_bits = RCC_CCIPR_LPTIM1SEL_LSI;
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_STM32L4_LPTIM2
|
|
case STM32L4_LPTIM2_BASE:
|
|
ccr_bits = RCC_CCIPR_LPTIM2SEL_LSI;
|
|
break;
|
|
#endif
|
|
}
|
|
break;
|
|
case STM32L4_LPTIM_CLK_LSE:
|
|
switch (priv->base)
|
|
{
|
|
#ifdef CONFIG_STM32L4_LPTIM1
|
|
case STM32L4_LPTIM1_BASE:
|
|
ccr_bits = RCC_CCIPR_LPTIM1SEL_LSE;
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_STM32L4_LPTIM2
|
|
case STM32L4_LPTIM2_BASE:
|
|
ccr_bits = RCC_CCIPR_LPTIM2SEL_LSE;
|
|
break;
|
|
#endif
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
modifyreg32(STM32L4_RCC_CCIPR, ccr_mask, ccr_bits);
|
|
|
|
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK,
|
|
LPTIM_CFGR_CKSEL_INTCLK);
|
|
}
|
|
|
|
return OK;
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: stm32l4_lptim_setperiod
|
|
************************************************************************************/
|
|
|
|
static void stm32l4_lptim_setperiod(FAR struct stm32l4_lptim_dev_s *dev,
|
|
uint32_t period)
|
|
{
|
|
FAR struct stm32l4_lptim_priv_s *priv = (FAR struct stm32l4_lptim_priv_s *)dev;
|
|
|
|
DEBUGASSERT(dev != NULL);
|
|
putreg32(period, (uintptr_t)(priv->base + STM32L4_LPTIM_ARR_OFFSET));
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: stm32l4_tim_getperiod
|
|
************************************************************************************/
|
|
|
|
static uint32_t stm32l4_lptim_getperiod(FAR struct stm32l4_lptim_dev_s *dev)
|
|
{
|
|
FAR struct stm32l4_lptim_priv_s *priv = (FAR struct stm32l4_lptim_priv_s *)dev;
|
|
|
|
DEBUGASSERT(dev != NULL);
|
|
return getreg32((uintptr_t)(priv->base + STM32L4_LPTIM_ARR_OFFSET));
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: stm32l4_lptim_setcountmode
|
|
************************************************************************************/
|
|
|
|
static int stm32l4_lptim_setcountmode(FAR struct stm32l4_lptim_dev_s *dev,
|
|
stm32l4_lptim_cntmode_t cntmode)
|
|
{
|
|
DEBUGASSERT(dev != NULL);
|
|
|
|
if (cntmode == STM32L4_LPTIM_COUNT_CLOCK)
|
|
{
|
|
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET,
|
|
LPTIM_CFGR_COUNTMODE, 0);
|
|
}
|
|
else if (cntmode == STM32L4_LPTIM_COUNT_EXTTRIG)
|
|
{
|
|
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET,
|
|
0, LPTIM_CFGR_COUNTMODE);
|
|
}
|
|
else
|
|
{
|
|
return ERROR;
|
|
}
|
|
|
|
return OK;
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: stm32l4_lptim_setpolarity
|
|
************************************************************************************/
|
|
|
|
static int stm32l4_lptim_setpolarity(FAR struct stm32l4_lptim_dev_s *dev,
|
|
stm32l4_lptim_clkpol_t polarity)
|
|
{
|
|
DEBUGASSERT(dev != NULL);
|
|
|
|
switch (polarity)
|
|
{
|
|
case STM32L4_LPTIM_CLKPOL_RISING:
|
|
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK,
|
|
LPTIM_CFGR_CKPOL_RISING);
|
|
break;
|
|
|
|
case STM32L4_LPTIM_CLKPOL_FALLING:
|
|
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK,
|
|
LPTIM_CFGR_CKPOL_FALLING);
|
|
break;
|
|
|
|
case STM32L4_LPTIM_CLKPOL_BOTH:
|
|
stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK,
|
|
LPTIM_CFGR_CKPOL_BOTH);
|
|
break;
|
|
}
|
|
|
|
return OK;
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: stm32l4_lptim_setpolarity
|
|
************************************************************************************/
|
|
|
|
static uint32_t stm32l4_lptim_getcounter(FAR struct stm32l4_lptim_dev_s *dev)
|
|
{
|
|
FAR struct stm32l4_lptim_priv_s *priv = (FAR struct stm32l4_lptim_priv_s *)dev;
|
|
|
|
DEBUGASSERT(dev != NULL);
|
|
|
|
uint32_t counter1;
|
|
uint32_t counter2;
|
|
|
|
do
|
|
{
|
|
counter1 = getreg32((uintptr_t)(priv->base + STM32L4_LPTIM_CNT_OFFSET));
|
|
counter2 = getreg32((uintptr_t)(priv->base + STM32L4_LPTIM_CNT_OFFSET));
|
|
}
|
|
while (counter1 != counter2);
|
|
|
|
return counter1;
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Public Functions
|
|
************************************************************************************/
|
|
|
|
/************************************************************************************
|
|
* Name: stm32l4_lptim_init
|
|
************************************************************************************/
|
|
|
|
FAR struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer)
|
|
{
|
|
struct stm32l4_lptim_dev_s *dev = NULL;
|
|
|
|
/* Get structure and enable power */
|
|
|
|
dev = stm32l4_lptim_getstruct(timer);
|
|
if (!dev)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
/* Is device already allocated */
|
|
|
|
if (((struct stm32l4_lptim_priv_s *)dev)->mode != STM32L4_LPTIM_MODE_UNUSED)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
/* Enable power */
|
|
|
|
stm32l4_lptim_enable(dev);
|
|
|
|
/* Reset timer */
|
|
|
|
stm32l4_lptim_reset(dev);
|
|
|
|
/* Mark it as used */
|
|
|
|
((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_DISABLED;
|
|
|
|
return dev;
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: stm32l4_lptim_deinit
|
|
************************************************************************************/
|
|
|
|
int stm32l4_lptim_deinit(FAR struct stm32l4_lptim_dev_s * dev)
|
|
{
|
|
DEBUGASSERT(dev);
|
|
|
|
/* Disable power */
|
|
|
|
stm32l4_lptim_disable(dev);
|
|
|
|
/* Mark it as free */
|
|
|
|
((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_UNUSED;
|
|
|
|
return OK;
|
|
}
|
|
|
|
#endif /* CONFIG_STM32L4_LPTIM1 || CONFIG_STM32L4_LPTIM2 */
|