743 lines
22 KiB
C
743 lines
22 KiB
C
/****************************************************************************
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* arch/arm/src/armv7-r/mpu.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV7R_MPU_H
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#define __ARCH_ARM_SRC_ARMV7R_MPU_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <sys/types.h>
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# include <stdint.h>
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# include <stdbool.h>
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# include <debug.h>
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# include "up_arch.h"
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# include "cp15.h"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* MPU Type Register Bit Definitions */
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#define MPUIR_SEPARATE (1 << 0) /* Bit 0: 0:unified or 1:separate memory maps */
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#define MPUIR_DREGION_SHIFT (8) /* Bits 8-15: Number MPU data regions */
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#define MPUIR_DREGION_MASK (0xff << MPUIR_DREGION_SHIFT)
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#define MPUIR_IREGION_SHIFT (16) /* Bits 16-23: Number MPU instruction regions */
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#define MPUIR_IREGION_MASK (0xff << MPUIR_IREGION_SHIFT)
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/* Region Base Address Register Definitions */
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#define MPU_RBAR_MASK 0xfffffffc
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/* Region Size and Enable Register */
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#define MPU_RASR_ENABLE (1 << 0) /* Bit 0: Region enable */
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#define MPU_RASR_RSIZE_SHIFT (1) /* Bits 1-5: Size of the MPU protection region */
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#define MPU_RASR_RSIZE_MASK (31 << MPU_RASR_RSIZE_SHIFT)
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# define MPU_RASR_RSIZE_LOG2(n) ((n-1) << MPU_RASR_RSIZE_SHIFT)
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#define MPU_RASR_SRD_SHIFT (8) /* Bits 8-15: Subregion disable */
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#define MPU_RASR_SRD_MASK (0xff << MPU_RASR_SRD_SHIFT)
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# define MPU_RASR_SRD_0 (0x01 << MPU_RASR_SRD_SHIFT)
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# define MPU_RASR_SRD_1 (0x02 << MPU_RASR_SRD_SHIFT)
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# define MPU_RASR_SRD_2 (0x04 << MPU_RASR_SRD_SHIFT)
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# define MPU_RASR_SRD_3 (0x08 << MPU_RASR_SRD_SHIFT)
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# define MPU_RASR_SRD_4 (0x10 << MPU_RASR_SRD_SHIFT)
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# define MPU_RASR_SRD_5 (0x20 << MPU_RASR_SRD_SHIFT)
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# define MPU_RASR_SRD_6 (0x40 << MPU_RASR_SRD_SHIFT)
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# define MPU_RASR_SRD_7 (0x80 << MPU_RASR_SRD_SHIFT)
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/* Region Access Control Register */
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#define MPU_RACR_B (1 << 0) /* Bit 0: Bufferable */
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#define MPU_RACR_C (1 << 1) /* Bit 1: Cacheable */
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#define MPU_RACR_S (1 << 2) /* Bit 2: Shareable */
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#define MPU_RACR_TEX_SHIFT (8) /* Bits 0-2: Memory attributes (with C and B) */
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#define MPU_RACR_TEX_MASK (7 << MPU_RACR_TEX_SHIFT)
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# define MPU_RACR_TEX(n) ((uint32_t)(n) << MPU_RACR_TEX_SHIFT)
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#define MPU_RACR_AP_SHIFT (8) /* Bits 8-10: Access permission */
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#define MPU_RACR_AP_MASK (7 << MPU_RACR_AP_SHIFT)
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# define MPU_RACR_AP_NONO (0 << MPU_RACR_AP_SHIFT) /* PL0:None PL1:None */
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# define MPU_RACR_AP_RWNO (1 << MPU_RACR_AP_SHIFT) /* PL0:RW PL1:None */
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# define MPU_RACR_AP_RWRO (2 << MPU_RACR_AP_SHIFT) /* PL0:RW PL1:RO */
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# define MPU_RACR_AP_RWRW (3 << MPU_RACR_AP_SHIFT) /* PL0:RW PL1:RW */
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# define MPU_RACR_AP_RONO (5 << MPU_RACR_AP_SHIFT) /* PL0:RO PL1:None */
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# define MPU_RACR_AP_RORO (6 << MPU_RACR_AP_SHIFT) /* PL0:RO PL1:RO */
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#define MPU_RACR_XN (1 << 12) /* Bit 12: Instruction access disable */
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/* MPU Region Number Register */
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#if defined(CONFIG_ARM_MPU_NREGIONS)
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# if CONFIG_ARM_MPU_NREGIONS <= 8
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# define MPU_RGNR_MASK (0x00000007)
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# elif CONFIG_ARM_MPU_NREGIONS <= 16
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# define MPU_RGNR_MASK (0x0000000f)
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# elif CONFIG_ARM_MPU_NREGIONS <= 32
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# define MPU_RGNR_MASK (0x0000001f)
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# else
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# error "FIXME: Unsupported number of MPU regions"
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# endif
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Name: mpu_allocregion
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*
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* Description:
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* Allocate the next region
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*
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****************************************************************************/
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unsigned int mpu_allocregion(void);
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/****************************************************************************
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* Name: mpu_log2regionceil
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*
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* Description:
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* Determine the smallest value of l2size (log base 2 size) such that the
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* following is true:
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*
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* size <= (1 << l2size)
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*
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****************************************************************************/
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uint8_t mpu_log2regionceil(size_t size);
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/****************************************************************************
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* Name: mpu_log2regionfloor
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*
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* Description:
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* Determine the largest value of l2size (log base 2 size) such that the
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* following is true:
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*
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* size >= (1 << l2size)
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*
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****************************************************************************/
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uint8_t mpu_log2regionfloor(size_t size);
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/****************************************************************************
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* Name: mpu_subregion
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*
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* Description:
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* Given (1) the offset to the beginning of valid data, (2) the size of the
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* memory to be mapped and (2) the log2 size of the mapping to use, determine
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* the minimal sub-region set to span that memory region.
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*
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* Assumption:
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* l2size has the same properties as the return value from
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* mpu_log2regionceil()
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*
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****************************************************************************/
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uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size);
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Name: mpu_get_mpuir
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*
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* Description:
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* Read the MPUIR register the characteristics of the MPU
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*
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****************************************************************************/
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static inline unsigned int mpu_get_mpuir(void)
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{
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unsigned int mpuir;
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__asm__ __volatile__
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(
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"\tmrc " CP15_MPUIR(%0)
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: "=r" (mpuir)
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:
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: "memory"
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);
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return mpuir;
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}
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/****************************************************************************
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* Name: mpu_set_drbar
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*
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* Description:
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* Wrtie to the DRBAR register
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*
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****************************************************************************/
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static inline void mpu_set_drbar(unsigned int drbar)
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{
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__asm__ __volatile__
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(
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"\tmcr " CP15_DRBAR(%0)
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:
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: "r" (drbar)
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: "memory"
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);
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}
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/****************************************************************************
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* Name: mpu_set_drsr
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*
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* Description:
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* Wrtie to the DRSR register
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*
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****************************************************************************/
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static inline void mpu_set_drsr(unsigned int drsr)
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{
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__asm__ __volatile__
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(
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"\tmcr " CP15_DRSR(%0)
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:
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: "r" (drsr)
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: "memory"
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);
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}
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/****************************************************************************
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* Name: mpu_set_dracr
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*
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* Description:
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* Wrtie to the DRACR register
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*
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****************************************************************************/
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static inline void mpu_set_dracr(unsigned int dracr)
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{
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__asm__ __volatile__
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(
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"\tmcr " CP15_DRACR(%0)
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:
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: "r" (dracr)
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: "memory"
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);
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}
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/****************************************************************************
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* Name: mpu_set_irbar
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*
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* Description:
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* Wrtie to the IRBAR register
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*
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****************************************************************************/
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#ifndef CONFIG_ARM_HAVE_MPU_UNIFIED
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static inline void mpu_set_irbar(unsigned int irbar)
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{
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__asm__ __volatile__
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(
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"\tmcr " CP15_IRBAR(%0)
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:
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: "r" (irbar)
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: "memory"
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);
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}
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#endif
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/****************************************************************************
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* Name: mpu_set_irsr
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*
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* Description:
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* Wrtie to the IRSR register
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*
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****************************************************************************/
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#ifndef CONFIG_ARM_HAVE_MPU_UNIFIED
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static inline void mpu_set_irsr(unsigned int irsr)
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{
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__asm__ __volatile__
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(
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"\tmcr " CP15_IRSR(%0)
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:
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: "r" (irsr)
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: "memory"
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);
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}
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#endif
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/****************************************************************************
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* Name: mpu_set_iracr
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*
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* Description:
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* Wrtie to the IRCR register
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*
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****************************************************************************/
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#ifndef CONFIG_ARM_HAVE_MPU_UNIFIED
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static inline void mpu_set_iracr(unsigned int iracr)
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{
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__asm__ __volatile__
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(
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"\tmcr " CP15_IRACR(%0)
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:
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: "r" (iracr)
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: "memory"
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);
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}
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#endif
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/****************************************************************************
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* Name: mpu_set_rgnr
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*
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* Description:
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* Wrtie to the IRCR register
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*
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****************************************************************************/
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static inline void mpu_set_rgnr(unsigned int rgnr)
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{
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__asm__ __volatile__
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(
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"\tmcr " CP15_RGNR(%0)
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:
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: "r" (rgnr)
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: "memory"
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);
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}
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/****************************************************************************
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* Name: mpu_showtype
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*
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* Description:
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* Show the characteristics of the MPU
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*
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****************************************************************************/
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static inline void mpu_showtype(void)
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{
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#ifdef CONFIG_DEBUG_SCHED_INFO
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uint32_t regval = mpu_get_mpuir();
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sinfo("%s MPU Regions: data=%d instr=%d\n",
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(regval & MPUIR_SEPARATE) != 0 ? "Separate" : "Unified",
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(regval & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT,
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(regval & MPUIR_IREGION_MASK) >> MPUIR_IREGION_SHIFT);
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#endif
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}
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/****************************************************************************
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* Name: mpu_control
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*
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* Description:
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* Enable (or disable) the MPU
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*
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****************************************************************************/
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static inline void mpu_control(bool enable)
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{
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uint32_t regval;
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/* Set/clear the following bits in the SCTLR:
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*
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* SCTLR_M Bit 0: MPU enable bit
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* SCTLR_BR Bit 17: Background Region bit (not cleared)
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*/
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regval = cp15_rdsctlr();
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if (enable)
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{
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regval |= (SCTLR_M | SCTLR_BR);
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cp15_wrsctlr(regval);
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}
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else
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{
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regval &= ~SCTLR_M;
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}
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cp15_wrsctlr(regval);
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}
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/****************************************************************************
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* Name: mpu_priv_stronglyordered
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*
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* Description:
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* Configure a region for privileged, strongly ordered memory
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*
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****************************************************************************/
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#if defined(CONFIG_ARMV7M_HAVE_ICACHE) || defined(CONFIG_ARMV7M_DCACHE)
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static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
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{
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unsigned int region = mpu_allocregion();
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uint32_t regval;
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uint8_t l2size;
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uint8_t subregions;
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/* Select the region */
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mpu_set_rgnr(region);
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/* Select the region base address */
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mpu_set_drbar(base & MPU_RBAR_ADDR_MASK) | region | MPU_RBAR_VALID);
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/* Select the region size and the sub-region map */
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l2size = mpu_log2regionceil(size);
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subregions = mpu_subregion(base, size, l2size);
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/* The configure the region */
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regval = /* Not Cacheable */
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/* Not Bufferable */
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MPU_RACR_S | /* Shareable */
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MPU_RACR_AP_RWNO; /* P:RW U:None */
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mpu_set_dracr(regval);
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regval = MPU_RASR_ENABLE | /* Enable region */
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MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
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((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
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mpu_set_drsr(regval);
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}
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#endif
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/****************************************************************************
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* Name: mpu_user_flash
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*
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* Description:
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* Configure a region for user program flash
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*
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****************************************************************************/
|
|
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static inline void mpu_user_flash(uintptr_t base, size_t size)
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{
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unsigned int region = mpu_allocregion();
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uint32_t regval;
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uint8_t l2size;
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uint8_t subregions;
|
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/* Select the region */
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mpu_set_rgnr(region);
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/* Select the region base address */
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mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
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/* Select the region size and the sub-region map */
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l2size = mpu_log2regionceil(size);
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subregions = mpu_subregion(base, size, l2size);
|
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/* The configure the region */
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regval = /* Not Cacheable */
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MPU_RACR_C | /* Cacheable */
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MPU_RACR_AP_RORO; /* P:RO U:RO */
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mpu_set_dracr(regval);
|
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|
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regval = MPU_RASR_ENABLE | /* Enable region */
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MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
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((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
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mpu_set_drsr(regval);
|
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}
|
|
|
|
/****************************************************************************
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|
* Name: mpu_priv_flash
|
|
*
|
|
* Description:
|
|
* Configure a region for privileged program flash
|
|
*
|
|
****************************************************************************/
|
|
|
|
static inline void mpu_priv_flash(uintptr_t base, size_t size)
|
|
{
|
|
unsigned int region = mpu_allocregion();
|
|
uint32_t regval;
|
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uint8_t l2size;
|
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uint8_t subregions;
|
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|
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/* Select the region */
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|
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mpu_set_rgnr(region);
|
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|
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/* Select the region base address */
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|
|
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mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
|
|
|
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/* Select the region size and the sub-region map */
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|
|
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l2size = mpu_log2regionceil(size);
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subregions = mpu_subregion(base, size, l2size);
|
|
|
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/* The configure the region */
|
|
|
|
regval = MPU_RACR_C | /* Cacheable */
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MPU_RACR_AP_RONO; /* P:RO U:None */
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mpu_set_dracr(regval);
|
|
|
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regval = MPU_RASR_ENABLE | /* Enable region */
|
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MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
|
|
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
|
|
mpu_set_drsr(regval);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: mpu_user_intsram
|
|
*
|
|
* Description:
|
|
* Configure a region as user internal SRAM
|
|
*
|
|
****************************************************************************/
|
|
|
|
static inline void mpu_user_intsram(uintptr_t base, size_t size)
|
|
{
|
|
unsigned int region = mpu_allocregion();
|
|
uint32_t regval;
|
|
uint8_t l2size;
|
|
uint8_t subregions;
|
|
|
|
/* Select the region */
|
|
|
|
mpu_set_rgnr(region);
|
|
|
|
/* Select the region base address */
|
|
|
|
mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
|
|
|
|
/* Select the region size and the sub-region map */
|
|
|
|
l2size = mpu_log2regionceil(size);
|
|
subregions = mpu_subregion(base, size, l2size);
|
|
|
|
/* The configure the region */
|
|
|
|
regval = MPU_RACR_S | /* Shareable */
|
|
MPU_RACR_C | /* Cacheable */
|
|
MPU_RACR_AP_RWRW; /* P:RW U:RW */
|
|
mpu_set_dracr(regval);
|
|
|
|
regval = MPU_RASR_ENABLE | /* Enable region */
|
|
MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
|
|
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
|
|
mpu_set_drsr(regval);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: mpu_priv_intsram
|
|
*
|
|
* Description:
|
|
* Configure a region as privileged internal SRAM
|
|
*
|
|
****************************************************************************/
|
|
|
|
static inline void mpu_priv_intsram(uintptr_t base, size_t size)
|
|
{
|
|
unsigned int region = mpu_allocregion();
|
|
uint32_t regval;
|
|
uint8_t l2size;
|
|
uint8_t subregions;
|
|
|
|
/* Select the region */
|
|
|
|
mpu_set_rgnr(region);
|
|
|
|
/* Select the region base address */
|
|
|
|
mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
|
|
|
|
/* Select the region size and the sub-region map */
|
|
|
|
l2size = mpu_log2regionceil(size);
|
|
subregions = mpu_subregion(base, size, l2size);
|
|
|
|
/* The configure the region */
|
|
|
|
regval = MPU_RACR_S | /* Shareable */
|
|
MPU_RACR_C | /* Cacheable */
|
|
MPU_RACR_AP_RWNO; /* P:RW U:None */
|
|
mpu_set_dracr(regval);
|
|
|
|
regval = MPU_RASR_ENABLE | /* Enable region */
|
|
MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
|
|
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
|
|
mpu_set_drsr(regval);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: mpu_user_extsram
|
|
*
|
|
* Description:
|
|
* Configure a region as user external SRAM
|
|
*
|
|
****************************************************************************/
|
|
|
|
static inline void mpu_user_extsram(uintptr_t base, size_t size)
|
|
{
|
|
unsigned int region = mpu_allocregion();
|
|
uint32_t regval;
|
|
uint8_t l2size;
|
|
uint8_t subregions;
|
|
|
|
/* Select the region */
|
|
|
|
mpu_set_rgnr(region);
|
|
|
|
/* Select the region base address */
|
|
|
|
mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
|
|
|
|
/* Select the region size and the sub-region map */
|
|
|
|
l2size = mpu_log2regionceil(size);
|
|
subregions = mpu_subregion(base, size, l2size);
|
|
|
|
/* The configure the region */
|
|
|
|
regval = MPU_RACR_S | /* Shareable */
|
|
MPU_RACR_C | /* Cacheable */
|
|
MPU_RACR_B | /* Bufferable */
|
|
MPU_RACR_AP_RWRW; /* P:RW U:RW */
|
|
mpu_set_dracr(regval);
|
|
|
|
regval = MPU_RASR_ENABLE | /* Enable region */
|
|
MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
|
|
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
|
|
mpu_set_drsr(regval);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: mpu_priv_extsram
|
|
*
|
|
* Description:
|
|
* Configure a region as privileged external SRAM
|
|
*
|
|
****************************************************************************/
|
|
|
|
static inline void mpu_priv_extsram(uintptr_t base, size_t size)
|
|
{
|
|
unsigned int region = mpu_allocregion();
|
|
uint32_t regval;
|
|
uint8_t l2size;
|
|
uint8_t subregions;
|
|
|
|
/* Select the region */
|
|
|
|
mpu_set_rgnr(region);
|
|
|
|
/* Select the region base address */
|
|
|
|
mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
|
|
|
|
/* Select the region size and the sub-region map */
|
|
|
|
l2size = mpu_log2regionceil(size);
|
|
subregions = mpu_subregion(base, size, l2size);
|
|
|
|
/* The configure the region */
|
|
|
|
regval = MPU_RACR_S | /* Shareable */
|
|
MPU_RACR_C | /* Cacheable */
|
|
MPU_RACR_B | /* Bufferable */
|
|
MPU_RACR_AP_RWNO; /* P:RW U:None */
|
|
mpu_set_dracr(regval);
|
|
|
|
regval = MPU_RASR_ENABLE | /* Enable region */
|
|
MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
|
|
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
|
|
mpu_set_drsr(regval);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: mpu_peripheral
|
|
*
|
|
* Description:
|
|
* Configure a region as privileged periperal address space
|
|
*
|
|
****************************************************************************/
|
|
|
|
static inline void mpu_peripheral(uintptr_t base, size_t size)
|
|
{
|
|
unsigned int region = mpu_allocregion();
|
|
uint32_t regval;
|
|
uint8_t l2size;
|
|
uint8_t subregions;
|
|
|
|
/* Select the region */
|
|
|
|
mpu_set_rgnr(region);
|
|
|
|
/* Select the region base address */
|
|
|
|
mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
|
|
|
|
/* Select the region size and the sub-region map */
|
|
|
|
l2size = mpu_log2regionceil(size);
|
|
subregions = mpu_subregion(base, size, l2size);
|
|
|
|
/* Then configure the region */
|
|
|
|
regval = MPU_RACR_S | /* Shareable */
|
|
MPU_RACR_B | /* Bufferable */
|
|
MPU_RACR_AP_RWNO | /* P:RW U:None */
|
|
MPU_RACR_XN; /* Instruction access disable */
|
|
mpu_set_dracr(regval);
|
|
|
|
regval = MPU_RASR_ENABLE | /* Enable region */
|
|
MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */
|
|
((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */
|
|
mpu_set_drsr(regval);
|
|
}
|
|
|
|
#undef EXTERN
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
#endif /* __ARCH_ARM_SRC_ARMV7R_MPU_H */
|