277 lines
10 KiB
C
277 lines
10 KiB
C
/****************************************************************************
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* boards/arm/stm32l5/nucleo-l552ze/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The NUCLEO-L552ZE-Q supports both HSE and LSE crystals (X2 and X3).
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* However, as shipped, the X3 crystal is not populated. Therefore the
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* Nucleo-L552ZE-Q will need to run off the 16MHz HSI clock, or the
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* 32kHz-synced MSI. This configuration uses the MSI.
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*
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* System Clock source : PLL (MSI)
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* SYSCLK(Hz) : 110000000 Determined by PLL configuration
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* HCLK(Hz) : 110000000 (STM32L5_RCC_CFGR_HPRE) (Max 110MHz)
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* AHB Prescaler : 1 (STM32L5_RCC_CFGR_HPRE) (Max 110MHz)
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* APB1 Prescaler : 1 (STM32L5_RCC_CFGR_PPRE1) (Max 110MHz)
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* APB2 Prescaler : 1 (STM32L5_RCC_CFGR_PPRE2) (Max 110MHz)
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* MSI Frequency(Hz) : 4000000 (nominal)
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* PLLM : 1 (STM32L5_PLLCFG_PLLM)
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* PLLN : 55 (STM32L5_PLLCFG_PLLN)
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* PLLP : 0 (STM32L5_PLLCFG_PLLP)
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* PLLQ : 0 (STM32L5_PLLCFG_PLLQ)
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* PLLR : 2 (STM32L5_PLLCFG_PLLR)
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* Flash Latency(WS) : 5
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* MSI - 4 MHz, autotrimmed via LSE
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* HSE - not installed
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* LSE - 32.768 kHz installed
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*/
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#define STM32L5_HSI_FREQUENCY 16000000ul
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#define STM32L5_LSI_FREQUENCY 32000
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#define STM32L5_LSE_FREQUENCY 32768
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#define STM32L5_BOARD_USEMSI 1
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#define STM32L5_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M
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/* prescaler common to all PLL inputs */
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#define STM32L5_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock */
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#define STM32L5_PLLCFG_PLLN RCC_PLLCFG_PLLN(55)
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#define STM32L5_PLLCFG_PLLP 0
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#undef STM32L5_PLLCFG_PLLP_ENABLED
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#define STM32L5_PLLCFG_PLLQ 0
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#undef STM32L5_PLLCFG_PLLQ_ENABLED
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#define STM32L5_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
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#define STM32L5_PLLCFG_PLLR_ENABLED
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/* 'SAIPLL1' is not used in this application */
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#define STM32L5_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24)
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#define STM32L5_PLLSAI1CFG_PLLP 0
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#undef STM32L5_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L5_PLLSAI1CFG_PLLQ 0
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#undef STM32L5_PLLSAI1CFG_PLLQ_ENABLED
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#define STM32L5_PLLSAI1CFG_PLLR 0
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#undef STM32L5_PLLSAI1CFG_PLLR_ENABLED
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/* 'SAIPLL2' is not used in this application */
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#define STM32L5_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
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#define STM32L5_PLLSAI2CFG_PLLP 0
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#undef STM32L5_PLLSAI2CFG_PLLP_ENABLED
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#define STM32L5_PLLSAI2CFG_PLLR 0
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#undef STM32L5_PLLSAI2CFG_PLLR_ENABLED
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#define STM32L5_SYSCLK_FREQUENCY 110000000ul
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/* Enable CLK48; get it from HSI48 */
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#if defined(CONFIG_STM32L5_USBFS) || defined(CONFIG_STM32L5_RNG)
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# define STM32L5_USE_CLK48 1
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# define STM32L5_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48
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# define STM32L5_HSI48_SYNCSRC SYNCSRC_NONE
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#endif
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/* Enable LSE (for the RTC and for MSI autotrimming) */
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#define STM32L5_USE_LSE 1
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/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
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#define STM32L5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32L5_HCLK_FREQUENCY STM32L5_SYSCLK_FREQUENCY
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/* Configure the APB1 prescaler */
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#define STM32L5_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32L5_PCLK1_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1)
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#define STM32L5_APB1_TIM2_CLKIN (STM32L5_PCLK1_FREQUENCY)
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#define STM32L5_APB1_TIM3_CLKIN (STM32L5_PCLK1_FREQUENCY)
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#define STM32L5_APB1_TIM4_CLKIN (STM32L5_PCLK1_FREQUENCY)
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#define STM32L5_APB1_TIM5_CLKIN (STM32L5_PCLK1_FREQUENCY)
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#define STM32L5_APB1_TIM6_CLKIN (STM32L5_PCLK1_FREQUENCY)
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#define STM32L5_APB1_TIM7_CLKIN (STM32L5_PCLK1_FREQUENCY)
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/* Configure the APB2 prescaler */
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#define STM32L5_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32L5_PCLK2_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1)
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#define STM32L5_APB2_TIM1_CLKIN (STM32L5_PCLK2_FREQUENCY)
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#define STM32L5_APB2_TIM15_CLKIN (STM32L5_PCLK2_FREQUENCY)
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#define STM32L5_APB2_TIM16_CLKIN (STM32L5_PCLK2_FREQUENCY)
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/* The timer clock frequencies are automatically defined by hardware. If the
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* APB prescaler equals 1, the timer clock frequencies are set to the same
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* frequency as that of the APB domain. Otherwise they are set to twice.
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* Note: TIM1,15,16 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32L5_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY STM32L5_HCLK_FREQUENCY
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#define BOARD_TIM3_FREQUENCY STM32L5_HCLK_FREQUENCY
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#define BOARD_TIM4_FREQUENCY STM32L5_HCLK_FREQUENCY
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#define BOARD_TIM5_FREQUENCY STM32L5_HCLK_FREQUENCY
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#define BOARD_TIM6_FREQUENCY STM32L5_HCLK_FREQUENCY
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#define BOARD_TIM7_FREQUENCY STM32L5_HCLK_FREQUENCY
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#define BOARD_TIM15_FREQUENCY STM32L5_HCLK_FREQUENCY
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#define BOARD_TIM16_FREQUENCY STM32L5_HCLK_FREQUENCY
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#define BOARD_LPTIM1_FREQUENCY STM32L5_HCLK_FREQUENCY
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#define BOARD_LPTIM2_FREQUENCY STM32L5_HCLK_FREQUENCY
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/* DMA Channel/Stream Selections ********************************************/
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/* Alternate function pin selections ****************************************/
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/* USART3: Connected to Arduino connector D0/D1 (or to STLink VCP if solder
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* bridges SB123 to SB130 are re-worked accordingly).
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*/
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#define GPIO_USART3_RX GPIO_USART3_RX_4 /* PD9 */
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#define GPIO_USART3_TX GPIO_USART3_TX_4 /* PD8 */
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/* LED definitions **********************************************************/
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/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED,
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* LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
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* The following definitions assume the default Solder Bridges are installed.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs
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* in any way.
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* The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_LED3 2
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#define BOARD_NLEDS 3
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#define BOARD_LED_GREEN BOARD_LED1
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#define BOARD_LED_BLUE BOARD_LED2
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#define BOARD_LED_RED BOARD_LED3
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED3_BIT (1 << BOARD_LED3)
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/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
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* include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS-
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* related events as follows:
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*
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*
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* SYMBOL Meaning LED state
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* Red Green Blue
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* ---------------------- -------------------------- ------ ------ ----
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*/
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#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
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#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
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#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
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#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
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#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */
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#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
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#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */
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#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */
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#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
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/* Thus if the Green LED is statically on, NuttX has successfully booted and
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* is, apparently, running normally. If the Red LED is flashing at
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* approximately 2Hz, then a fatal error has been detected and the system
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* has halted.
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*/
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/* Button definitions *******************************************************/
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/* The Nucleo-L552ZE supports one button: Pushbutton B1, labeled "User", is
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* connected to GPIO PC13.
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* A high value will be sensed when the button is pressed.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: stm32l5_board_initialize
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*
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* Description:
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* All STM32L5 architectures must provide the following entry point.
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* This entry point is called early in the initialization -- after all
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* memory has been configured and mapped but before any devices
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* have been initialized.
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*
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****************************************************************************/
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void stm32l5_board_initialize(void);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_INCLUDE_BOARD_H */
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