e3b3e57e56
New interface allows checking if RTC time has been set. This allows to application to detect if RTC has valid time (after reset) or should application attempt to get real time by other means (for example, by launching ntpclient or GPS).
1527 lines
41 KiB
C
1527 lines
41 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/stm32f40xxx_rtcc.c
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*
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* Copyright (C) 2012-2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Modified: Neil Hancock
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdbool.h>
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#include <sched.h>
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#include <time.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include "up_arch.h"
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#include "stm32_rcc.h"
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#include "stm32_pwr.h"
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#include "stm32_exti.h"
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#include "stm32_rtc.h"
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#include <arch/board/board.h>
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#ifdef CONFIG_RTC
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* This RTC implementation supports
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* - date/time RTC hardware
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* - extended functions Alarm A and B for STM32F4xx and onwards
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* */
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#ifndef CONFIG_RTC_DATETIME
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# error "CONFIG_RTC_DATETIME must be set to use this driver"
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#endif
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#ifdef CONFIG_RTC_HIRES
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# error "CONFIG_RTC_HIRES must NOT be set with this driver"
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#endif
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#ifndef CONFIG_STM32_PWR
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# error "CONFIG_STM32_PWR must selected to use this driver"
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#endif
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/* Constants ****************************************************************/
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#define SYNCHRO_TIMEOUT (0x00020000)
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#define INITMODE_TIMEOUT (0x00010000)
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/* Proxy definitions to make the same code work for all the STM32 series ****/
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# define STM32_RCC_XXX STM32_RCC_BDCR
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# define RCC_XXX_YYYRST RCC_BDCR_BDRST
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# define RCC_XXX_RTCEN RCC_BDCR_RTCEN
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# define RCC_XXX_RTCSEL_MASK RCC_BDCR_RTCSEL_MASK
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# define RCC_XXX_RTCSEL_LSE RCC_BDCR_RTCSEL_LSE
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# define RCC_XXX_RTCSEL_LSI RCC_BDCR_RTCSEL_LSI
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# define RCC_XXX_RTCSEL_HSE RCC_BDCR_RTCSEL_HSE
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/* Time conversions */
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#define MINUTES_IN_HOUR 60
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#define HOURS_IN_DAY 24
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#define hours_add(parm_hrs) \
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time->tm_hour += parm_hrs;\
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if ((HOURS_IN_DAY-1) < (time->tm_hour))\
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{\
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time->tm_hour = (parm_hrs - HOURS_IN_DAY);\
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}
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#define RTC_ALRMR_DIS_MASK (RTC_ALRMR_MSK4 | RTC_ALRMR_MSK3 | \
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RTC_ALRMR_MSK2 | RTC_ALRMR_MSK1)
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#define RTC_ALRMR_DIS_DATE_MASK (RTC_ALRMR_MSK4)
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#define RTC_ALRMR_ENABLE (0)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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#ifdef CONFIG_RTC_ALARM
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typedef unsigned int rtc_alarmreg_t;
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struct alm_cbinfo_s
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{
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volatile alm_callback_t ac_cb; /* Client callback function */
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volatile FAR void *ac_arg; /* Argument to pass with the callback function */
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};
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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#ifdef CONFIG_RTC_ALARM
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/* Callback to use when an EXTI is activated */
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static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST];
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static bool g_alarm_enabled; /* True: Alarm interrupts are enabled */
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* g_rtc_enabled is set true after the RTC has successfully initialized */
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volatile bool g_rtc_enabled = false;
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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#ifdef CONFIG_RTC_ALARM
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static int rtchw_check_alrawf(void);
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static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg);
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#if CONFIG_RTC_NALARMS > 1
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static int rtchw_check_alrbwf(void);
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static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg);
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#endif
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static inline void rtc_enable_alarm(void);
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: rtc_dumpregs
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*
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* Description:
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* Disable RTC write protection
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_RTC_INFO
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static void rtc_dumpregs(FAR const char *msg)
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{
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int rtc_state;
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rtcinfo("%s:\n", msg);
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rtcinfo(" TR: %08x\n", getreg32(STM32_RTC_TR));
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rtcinfo(" DR: %08x\n", getreg32(STM32_RTC_DR));
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rtcinfo(" CR: %08x\n", getreg32(STM32_RTC_CR));
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rtcinfo(" ISR: %08x\n", getreg32(STM32_RTC_ISR));
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rtcinfo(" PRER: %08x\n", getreg32(STM32_RTC_PRER));
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rtcinfo(" WUTR: %08x\n", getreg32(STM32_RTC_WUTR));
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rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR));
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rtcinfo(" ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR));
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rtcinfo(" SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR));
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rtcinfo(" TSTR: %08x\n", getreg32(STM32_RTC_TSTR));
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rtcinfo(" TSDR: %08x\n", getreg32(STM32_RTC_TSDR));
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rtcinfo(" TSSSR: %08x\n", getreg32(STM32_RTC_TSSSR));
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rtcinfo(" CALR: %08x\n", getreg32(STM32_RTC_CALR));
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rtcinfo(" TAFCR: %08x\n", getreg32(STM32_RTC_TAFCR));
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rtcinfo("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR));
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rtcinfo("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR));
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rtcinfo("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG));
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rtc_state =
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((getreg32(STM32_EXTI_RTSR) & EXTI_RTC_ALARM) ? 0x1000 : 0) |
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((getreg32(STM32_EXTI_FTSR) & EXTI_RTC_ALARM) ? 0x0100 : 0) |
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((getreg32(STM32_EXTI_IMR) & EXTI_RTC_ALARM) ? 0x0010 : 0) |
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((getreg32(STM32_EXTI_EMR) & EXTI_RTC_ALARM) ? 0x0001 : 0);
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rtcinfo("EXTI (RTSR FTSR ISR EVT): %01x\n",rtc_state);
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}
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#else
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# define rtc_dumpregs(msg)
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#endif
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/****************************************************************************
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* Name: rtc_dumptime
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*
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* Description:
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* Disable RTC write protection
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_RTC_INFO
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static void rtc_dumptime(FAR const struct tm *tp, FAR const char *msg)
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{
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rtcinfo("%s:\n", msg);
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rtcinfo(" tm_sec: %08x\n", tp->tm_sec);
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rtcinfo(" tm_min: %08x\n", tp->tm_min);
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rtcinfo(" tm_hour: %08x\n", tp->tm_hour);
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rtcinfo(" tm_mday: %08x\n", tp->tm_mday);
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rtcinfo(" tm_mon: %08x\n", tp->tm_mon);
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rtcinfo(" tm_year: %08x\n", tp->tm_year);
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}
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#else
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# define rtc_dumptime(tp, msg)
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#endif
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/****************************************************************************
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* Name: rtc_wprunlock
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*
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* Description:
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* Disable RTC write protection
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void rtc_wprunlock(void)
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{
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/* Enable write access to the backup domain (RTC registers, RTC backup data
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* registers and backup SRAM).
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*/
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stm32_pwr_enablebkp(true);
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/* The following steps are required to unlock the write protection on all the
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* RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR).
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*
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* 1. Write 0xCA into the RTC_WPR register.
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* 2. Write 0x53 into the RTC_WPR register.
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*
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* Writing a wrong key re-activates the write protection.
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*/
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putreg32(0xca, STM32_RTC_WPR);
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putreg32(0x53, STM32_RTC_WPR);
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}
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/****************************************************************************
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* Name: rtc_wprlock
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*
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* Description:
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* Enable RTC write protection
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void rtc_wprlock(void)
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{
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/* Writing any wrong key re-activates the write protection. */
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putreg32(0xff, STM32_RTC_WPR);
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/* Disable write access to the backup domain (RTC registers, RTC backup
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* data registers and backup SRAM).
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*/
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stm32_pwr_enablebkp(false);
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}
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/****************************************************************************
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* Name: rtc_synchwait
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*
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* Description:
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* Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
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* synchronized with RTC APB clock.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Zero (OK) on success; a negated errno on failure
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*
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****************************************************************************/
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static int rtc_synchwait(void)
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{
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volatile uint32_t timeout;
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uint32_t regval;
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int ret;
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/* Disable the write protection for RTC registers */
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rtc_wprunlock();
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/* Clear Registers synchronization flag (RSF) */
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regval = getreg32(STM32_RTC_ISR);
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regval &= ~RTC_ISR_RSF;
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putreg32(regval, STM32_RTC_ISR);
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/* Now wait the registers to become synchronised */
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ret = -ETIMEDOUT;
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for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++)
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{
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regval = getreg32(STM32_RTC_ISR);
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if ((regval & RTC_ISR_RSF) != 0)
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{
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/* Synchronized */
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ret = OK;
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break;
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}
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}
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/* Re-enable the write protection for RTC registers */
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rtc_wprlock();
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return ret;
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}
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/****************************************************************************
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* Name: rtc_enterinit
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*
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* Description:
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* Enter RTC initialization mode.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Zero (OK) on success; a negated errno on failure
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*
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****************************************************************************/
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static int rtc_enterinit(void)
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{
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volatile uint32_t timeout;
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uint32_t regval;
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int ret;
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/* Check if the Initialization mode is already set */
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regval = getreg32(STM32_RTC_ISR);
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ret = OK;
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if ((regval & RTC_ISR_INITF) == 0)
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{
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/* Set the Initialization mode */
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putreg32(RTC_ISR_INIT, STM32_RTC_ISR);
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/* Wait until the RTC is in the INIT state (or a timeout occurs) */
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ret = -ETIMEDOUT;
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for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++)
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{
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regval = getreg32(STM32_RTC_ISR);
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if ((regval & RTC_ISR_INITF) != 0)
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{
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ret = OK;
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break;
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}
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}
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}
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return ret;
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}
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/****************************************************************************
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* Name: rtc_exitinit
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*
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* Description:
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* Exit RTC initialization mode.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Zero (OK) on success; a negated errno on failure
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*
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****************************************************************************/
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static void rtc_exitinit(void)
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{
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uint32_t regval;
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regval = getreg32(STM32_RTC_ISR);
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regval &= ~(RTC_ISR_INIT);
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putreg32(regval, STM32_RTC_ISR);
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}
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/****************************************************************************
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* Name: rtc_bin2bcd
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*
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* Description:
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* Converts a 2 digit binary to BCD format
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*
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* Input Parameters:
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* value - The byte to be converted.
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*
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* Returned Value:
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* The value in BCD representation
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*
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****************************************************************************/
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static uint32_t rtc_bin2bcd(int value)
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{
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uint32_t msbcd = 0;
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while (value >= 10)
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{
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msbcd++;
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value -= 10;
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}
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return (msbcd << 4) | value;
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}
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/****************************************************************************
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* Name: rtc_bin2bcd
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*
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* Description:
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* Convert from 2 digit BCD to binary.
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*
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* Input Parameters:
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* value - The BCD value to be converted.
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*
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* Returned Value:
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* The value in binary representation
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*
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****************************************************************************/
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static int rtc_bcd2bin(uint32_t value)
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{
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uint32_t tens = (value >> 4) * 10;
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return (int)(tens + (value & 0x0f));
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}
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|
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/****************************************************************************
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* Name: rtc_setup
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*
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* Description:
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* Performs first time configuration of the RTC. A special value written
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* into back-up register 0 will prevent this function from being called on
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* sub-sequent resets or power up.
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*
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* Input Parameters:
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* None
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|
*
|
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* Returned Value:
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* Zero (OK) on success; a negated errno on failure
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*
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****************************************************************************/
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static int rtc_setup(void)
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{
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uint32_t regval;
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int ret;
|
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/* Disable the write protection for RTC registers */
|
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rtc_wprunlock();
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|
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/* Set Initialization mode */
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ret = rtc_enterinit();
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if (ret == OK)
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{
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/* Set the 24 hour format by clearing the FMT bit in the RTC
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* control register
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*/
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regval = getreg32(STM32_RTC_CR);
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regval &= ~RTC_CR_FMT;
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putreg32(regval, STM32_RTC_CR);
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|
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/* Configure RTC pre-scaler with the required values */
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|
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#ifdef CONFIG_RTC_HSECLOCK
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/* For a 1 MHz clock this yields 0.9999360041 Hz on the second
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* timer - which is pretty close.
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*/
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putreg32(((uint32_t)7182 << RTC_PRER_PREDIV_S_SHIFT) |
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((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT),
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STM32_RTC_PRER);
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#else
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/* Correct values for 32.768 KHz LSE clock and inaccurate LSI clock */
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putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) |
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((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT),
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STM32_RTC_PRER);
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#endif
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|
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/* Exit RTC initialization mode */
|
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|
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rtc_exitinit();
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}
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|
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/* Re-enable the write protection for RTC registers */
|
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|
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rtc_wprlock();
|
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|
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return ret;
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}
|
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|
|
/****************************************************************************
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|
* Name: rtc_resume
|
|
*
|
|
* Description:
|
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* Called when the RTC was already initialized on a previous power cycle.
|
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* This just brings the RTC back into full operation.
|
|
*
|
|
* Input Parameters:
|
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* None
|
|
*
|
|
* Returned Value:
|
|
* Zero (OK) on success; a negated errno on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void rtc_resume(void)
|
|
{
|
|
#ifdef CONFIG_RTC_ALARM
|
|
uint32_t regval;
|
|
|
|
/* Clear the RTC alarm flags */
|
|
|
|
regval = getreg32(STM32_RTC_ISR);
|
|
regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF);
|
|
putreg32(regval, STM32_RTC_ISR);
|
|
|
|
/* Clear the RTC Alarm Pending bit */
|
|
|
|
putreg32(EXTI_RTC_ALARM, STM32_EXTI_PR);
|
|
#endif
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_rtc_alarm_handler
|
|
*
|
|
* Description:
|
|
* RTC ALARM interrupt service routine through the EXTI line
|
|
*
|
|
* Input Parameters:
|
|
* irq - The IRQ number that generated the interrupt
|
|
* context - Architecture specific register save information.
|
|
*
|
|
* Returned Value:
|
|
* Zero (OK) on success; A negated errno value on failure.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_RTC_ALARM
|
|
static int stm32_rtc_alarm_handler(int irq, void *context, void *arg)
|
|
{
|
|
FAR struct alm_cbinfo_s *cbinfo;
|
|
alm_callback_t cb;
|
|
FAR void *cb_arg;
|
|
uint32_t isr;
|
|
uint32_t cr;
|
|
int ret = OK;
|
|
|
|
isr = getreg32(STM32_RTC_ISR);
|
|
|
|
/* Check for EXTI from Alarm A or B and handle according */
|
|
|
|
if ((isr & RTC_ISR_ALRAF) != 0)
|
|
{
|
|
cr = getreg32(STM32_RTC_CR);
|
|
if ((cr & RTC_CR_ALRAIE) != 0)
|
|
{
|
|
cbinfo = &g_alarmcb[RTC_ALARMA];
|
|
if (cbinfo->ac_cb != NULL)
|
|
{
|
|
/* Alarm A callback */
|
|
|
|
cb = cbinfo->ac_cb;
|
|
cb_arg = (FAR void *)cbinfo->ac_arg;
|
|
|
|
cbinfo->ac_cb = NULL;
|
|
cbinfo->ac_arg = NULL;
|
|
|
|
cb(cb_arg, RTC_ALARMA);
|
|
}
|
|
|
|
isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF;
|
|
putreg32(isr, STM32_RTC_CR);
|
|
}
|
|
}
|
|
|
|
#if CONFIG_RTC_NALARMS > 1
|
|
if ((isr & RTC_ISR_ALRBF) != 0)
|
|
{
|
|
cr = getreg32(STM32_RTC_CR);
|
|
if ((cr & RTC_CR_ALRBIE) != 0)
|
|
{
|
|
cbinfo = &g_alarmcb[RTC_ALARMB];
|
|
if (cbinfo->ac_cb != NULL)
|
|
{
|
|
/* Alarm B callback */
|
|
|
|
cb = cbinfo->ac_cb;
|
|
cb_arg = (FAR void *)cbinfo->ac_arg;
|
|
|
|
cbinfo->ac_cb = NULL;
|
|
cbinfo->ac_arg = NULL;
|
|
|
|
cb(cb_arg, RTC_ALARMB);
|
|
}
|
|
|
|
isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF;
|
|
putreg32(isr, STM32_RTC_CR);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: rtchw_check_alrXwf X= a or B
|
|
*
|
|
* Description:
|
|
* Check registers
|
|
*
|
|
* Input Parameters:
|
|
* None
|
|
*
|
|
* Returned Value:
|
|
* Zero (OK) on success; a negated errno on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_RTC_ALARM
|
|
static int rtchw_check_alrawf(void)
|
|
{
|
|
volatile uint32_t timeout;
|
|
uint32_t regval;
|
|
int ret = -ETIMEDOUT;
|
|
|
|
/* Check RTC_ISR ALRAWF for access to alarm register,
|
|
* Can take 2 RTCCLK cycles or timeout
|
|
* CubeMX use GetTick.
|
|
*/
|
|
|
|
for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++)
|
|
{
|
|
regval = getreg32(STM32_RTC_ISR);
|
|
if ((regval & RTC_ISR_ALRAWF) != 0)
|
|
{
|
|
ret = OK;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1
|
|
static int rtchw_check_alrbwf(void)
|
|
{
|
|
volatile uint32_t timeout;
|
|
uint32_t regval;
|
|
int ret = -ETIMEDOUT;
|
|
|
|
/* Check RTC_ISR ALRAWF for access to alarm register,
|
|
* can take 2 RTCCLK cycles or timeout
|
|
* CubeMX use GetTick.
|
|
*/
|
|
|
|
for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++)
|
|
{
|
|
regval = getreg32(STM32_RTC_ISR);
|
|
if ((regval & RTC_ISR_ALRBWF) != 0)
|
|
{
|
|
ret = OK;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_rtchw_set_alrmXr X is a or b
|
|
*
|
|
* Description:
|
|
* Set the alarm (A or B) hardware registers, using the required hardware
|
|
* access protocol
|
|
*
|
|
* Input Parameters:
|
|
* alarmreg - the register
|
|
*
|
|
* Returned Value:
|
|
* Zero (OK) on success; a negated errno on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_RTC_ALARM
|
|
static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg)
|
|
{
|
|
int ret = -EBUSY;
|
|
|
|
/* Need to follow RTC register wrote protection
|
|
* Disable the write protection for RTC registers
|
|
*/
|
|
|
|
rtc_wprunlock();
|
|
|
|
/* Disable RTC alarm & Interrupt */
|
|
|
|
modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0);
|
|
|
|
ret = rtchw_check_alrawf();
|
|
if (ret != OK)
|
|
{
|
|
goto errout_with_wprunlock;
|
|
}
|
|
|
|
/* Set the RTC Alarm register */
|
|
|
|
putreg32(alarmreg, STM32_RTC_ALRMAR);
|
|
rtcinfo(" TR: %08x ALRMAR: %08x\n",
|
|
getreg32(STM32_RTC_TR), getreg32(STM32_RTC_ALRMAR));
|
|
|
|
/* Enable RTC alarm */
|
|
|
|
modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE));
|
|
|
|
errout_with_wprunlock:
|
|
rtc_wprlock();
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1
|
|
static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg)
|
|
{
|
|
int ret = -EBUSY;
|
|
|
|
/* Need to follow RTC register wrote protection
|
|
* Disable the write protection for RTC registers
|
|
*/
|
|
|
|
rtc_wprunlock();
|
|
|
|
/* Disable RTC alarm B & Interrupt B */
|
|
|
|
modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0);
|
|
|
|
ret = rtchw_check_alrbwf();
|
|
if (ret != OK)
|
|
{
|
|
goto rtchw_set_alrmbr_exit;
|
|
}
|
|
|
|
/* Set the RTC Alarm register */
|
|
|
|
putreg32(alarmreg, STM32_RTC_ALRMBR);
|
|
rtcinfo(" TR: %08x ALRMBR: %08x\n",
|
|
getreg32(STM32_RTC_TR), getreg32(STM32_RTC_ALRMBR));
|
|
|
|
/* Enable RTC alarm B */
|
|
|
|
modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE));
|
|
|
|
rtchw_set_alrmbr_exit:
|
|
rtc_wprlock();
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: rtc_enable_alarm
|
|
*
|
|
* Description:
|
|
* Enable ALARM interrupts
|
|
*
|
|
* Input Parameters:
|
|
* None
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_RTC_ALARM
|
|
static inline void rtc_enable_alarm(void)
|
|
{
|
|
/* Is the alarm already enabled? */
|
|
|
|
if (!g_alarm_enabled)
|
|
{
|
|
/* Configure RTC interrupt to catch alarm interrupts. All RTC
|
|
* interrupts are connected to the EXTI controller. To enable the
|
|
* RTC Alarm interrupt, the following sequence is required:
|
|
*
|
|
* 1. Configure and enable the EXTI Line 17 RTC ALARM in interrupt
|
|
* mode and select the rising edge sensitivity.
|
|
* For STM32F4xx
|
|
* EXTI line 21 RTC Tamper & Timestamp
|
|
* EXTI line 22 RTC Wakeup
|
|
* 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC.
|
|
* 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).
|
|
*/
|
|
|
|
(void)stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL);
|
|
g_alarm_enabled = true;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Public Functions
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: up_rtc_initialize
|
|
*
|
|
* Description:
|
|
* Initialize the hardware RTC per the selected configuration. This
|
|
* function is called once during the OS initialization sequence
|
|
*
|
|
* Input Parameters:
|
|
* None
|
|
*
|
|
* Returned Value:
|
|
* Zero (OK) on success; a negated errno on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
int up_rtc_initialize(void)
|
|
{
|
|
uint32_t regval;
|
|
uint32_t tr_bkp;
|
|
uint32_t dr_bkp;
|
|
int ret;
|
|
int maxretry = 10;
|
|
int nretry = 0;
|
|
|
|
/* Clocking for the PWR block must be provided. However, this is done
|
|
* unconditionally in stm32f40xxx_rcc.c on power up. This done
|
|
* unconditionally because the PWR block is also needed to set the
|
|
* internal voltage regulator for maximum performance.
|
|
*/
|
|
|
|
/* Select the clock source */
|
|
/* Save the token before losing it when resetting */
|
|
|
|
regval = getreg32(RTC_MAGIC_REG);
|
|
|
|
stm32_pwr_enablebkp(true);
|
|
|
|
if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET)
|
|
{
|
|
/* Some boards do not have the external 32khz oscillator installed,
|
|
* for those boards we must fallback to the crummy internal RC clock
|
|
* or the external high rate clock
|
|
*/
|
|
|
|
#ifdef CONFIG_RTC_HSECLOCK
|
|
/* Use the HSE clock as the input to the RTC block */
|
|
|
|
rtc_dumpregs("On reset HSE");
|
|
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE);
|
|
|
|
#elif defined(CONFIG_RTC_LSICLOCK)
|
|
/* Use the LSI clock as the input to the RTC block */
|
|
|
|
rtc_dumpregs("On reset LSI");
|
|
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI);
|
|
|
|
#elif defined(CONFIG_RTC_LSECLOCK)
|
|
/* Use the LSE clock as the input to the RTC block */
|
|
|
|
rtc_dumpregs("On reset LSE");
|
|
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE);
|
|
|
|
#endif
|
|
/* Enable the RTC Clock by setting the RTCEN bit in the RCC register */
|
|
|
|
modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_RTCEN);
|
|
}
|
|
else /* The RTC is already in use: check if the clock source is changed */
|
|
{
|
|
#if defined(CONFIG_RTC_HSECLOCK) || defined(CONFIG_RTC_LSICLOCK) || \
|
|
defined(CONFIG_RTC_LSECLOCK)
|
|
|
|
uint32_t clksrc = getreg32(STM32_RCC_XXX);
|
|
|
|
rtc_dumpregs("On reset warm");
|
|
|
|
#if defined(CONFIG_RTC_HSECLOCK)
|
|
if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_HSE)
|
|
#elif defined(CONFIG_RTC_LSICLOCK)
|
|
if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_LSI)
|
|
#elif defined(CONFIG_RTC_LSECLOCK)
|
|
if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_LSE)
|
|
#endif
|
|
#endif
|
|
{
|
|
tr_bkp = getreg32(STM32_RTC_TR);
|
|
dr_bkp = getreg32(STM32_RTC_DR);
|
|
modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST);
|
|
modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0);
|
|
|
|
#if defined(CONFIG_RTC_HSECLOCK)
|
|
/* Change to the new clock as the input to the RTC block */
|
|
|
|
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE);
|
|
|
|
#elif defined(CONFIG_RTC_LSICLOCK)
|
|
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI);
|
|
|
|
#elif defined(CONFIG_RTC_LSECLOCK)
|
|
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE);
|
|
#endif
|
|
|
|
putreg32(tr_bkp, STM32_RTC_TR);
|
|
putreg32(dr_bkp, STM32_RTC_DR);
|
|
|
|
/* Remember that the RTC is initialized */
|
|
|
|
putreg32(RTC_MAGIC, RTC_MAGIC_REG);
|
|
|
|
/* Enable the RTC Clock by setting the RTCEN bit in the RCC register */
|
|
|
|
modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_RTCEN);
|
|
}
|
|
}
|
|
|
|
stm32_pwr_enablebkp(false);
|
|
|
|
/* Loop, attempting to initialize/resume the RTC. This loop is necessary
|
|
* because it seems that occasionally it takes longer to initialize the RTC
|
|
* (the actual failure is in rtc_synchwait()).
|
|
*/
|
|
|
|
do
|
|
{
|
|
/* Wait for the RTC Time and Date registers to be synchronized with RTC
|
|
* APB clock.
|
|
*/
|
|
|
|
ret = rtc_synchwait();
|
|
|
|
/* Check that rtc_syncwait() returned successfully */
|
|
|
|
switch (ret)
|
|
{
|
|
case OK:
|
|
{
|
|
rtcinfo("rtc_syncwait() okay\n");
|
|
break;
|
|
}
|
|
|
|
default:
|
|
{
|
|
rtcerr("ERROR: rtc_syncwait() failed (%d)\n", ret);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
while (ret != OK && ++nretry < maxretry);
|
|
|
|
/* Check if the one-time initialization of the RTC has already been
|
|
* performed. We can determine this by checking if the magic number
|
|
* has been writing to to back-up date register DR0.
|
|
*/
|
|
|
|
if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET)
|
|
{
|
|
rtcinfo("Do setup\n");
|
|
|
|
/* Perform the one-time setup of the LSE clocking to the RTC */
|
|
|
|
ret = rtc_setup();
|
|
|
|
/* Enable write access to the backup domain (RTC registers, RTC
|
|
* backup data registers and backup SRAM).
|
|
*/
|
|
|
|
stm32_pwr_enablebkp(true);
|
|
|
|
/* Remember that the RTC is initialized */
|
|
|
|
putreg32(RTC_MAGIC, RTC_MAGIC_REG);
|
|
|
|
/* Disable write access to the backup domain (RTC registers, RTC
|
|
* backup data registers and backup SRAM).
|
|
*/
|
|
|
|
stm32_pwr_enablebkp(false);
|
|
}
|
|
else
|
|
{
|
|
rtcinfo("Do resume\n");
|
|
|
|
/* RTC already set-up, just resume normal operation */
|
|
|
|
rtc_resume();
|
|
rtc_dumpregs("Did resume");
|
|
}
|
|
|
|
if (ret != OK && nretry > 0)
|
|
{
|
|
rtcinfo("setup/resume ran %d times and failed with %d\n",
|
|
nretry, ret);
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
rtc_dumpregs("After Initialization");
|
|
|
|
g_rtc_enabled = true;
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_rtc_getdatetime_with_subseconds
|
|
*
|
|
* Description:
|
|
* Get the current date and time from the date/time RTC. This interface
|
|
* is only supported by the date/time RTC hardware implementation.
|
|
* It is used to replace the system timer. It is only used by the RTOS
|
|
* during initialization to set up the system time when CONFIG_RTC and
|
|
* CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not).
|
|
*
|
|
* NOTE: Some date/time RTC hardware is capability of sub-second accuracy.
|
|
* That sub-second accuracy is returned through 'nsec'.
|
|
*
|
|
* Input Parameters:
|
|
* tp - The location to return the high resolution time value.
|
|
* nsec - The location to return the subsecond time value.
|
|
*
|
|
* Returned Value:
|
|
* Zero (OK) on success; a negated errno on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
|
|
int stm32_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec)
|
|
#else
|
|
int up_rtc_getdatetime(FAR struct tm *tp)
|
|
#endif
|
|
{
|
|
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
|
|
uint32_t ssr;
|
|
#endif
|
|
uint32_t dr;
|
|
uint32_t tr;
|
|
uint32_t tmp;
|
|
|
|
/* Sample the data time registers. There is a race condition here... If
|
|
* we sample the time just before midnight on December 31, the date could
|
|
* be wrong because the day rolled over while were sampling.
|
|
*/
|
|
|
|
do
|
|
{
|
|
dr = getreg32(STM32_RTC_DR);
|
|
tr = getreg32(STM32_RTC_TR);
|
|
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
|
|
ssr = getreg32(STM32_RTC_SSR);
|
|
#endif
|
|
tmp = getreg32(STM32_RTC_DR);
|
|
}
|
|
while (tmp != dr);
|
|
|
|
rtc_dumpregs("Reading Time");
|
|
|
|
/* Convert the RTC time to fields in struct tm format. All of the STM32
|
|
* All of the ranges of values correspond between struct tm and the time
|
|
* register.
|
|
*/
|
|
|
|
tmp = (tr & (RTC_TR_SU_MASK | RTC_TR_ST_MASK)) >> RTC_TR_SU_SHIFT;
|
|
tp->tm_sec = rtc_bcd2bin(tmp);
|
|
|
|
tmp = (tr & (RTC_TR_MNU_MASK | RTC_TR_MNT_MASK)) >> RTC_TR_MNU_SHIFT;
|
|
tp->tm_min = rtc_bcd2bin(tmp);
|
|
|
|
tmp = (tr & (RTC_TR_HU_MASK | RTC_TR_HT_MASK)) >> RTC_TR_HU_SHIFT;
|
|
tp->tm_hour = rtc_bcd2bin(tmp);
|
|
|
|
/* Now convert the RTC date to fields in struct tm format:
|
|
* Days: 1-31 match in both cases.
|
|
* Month: STM32 is 1-12, struct tm is 0-11.
|
|
* Years: STM32 is 00-99, struct tm is years since 1900.
|
|
* WeekDay: STM32 is 1 = Mon - 7 = Sun
|
|
*
|
|
* Issue: I am not sure what the STM32 years mean. Are these the
|
|
* years 2000-2099? I'll assume so.
|
|
*/
|
|
|
|
tmp = (dr & (RTC_DR_DU_MASK | RTC_DR_DT_MASK)) >> RTC_DR_DU_SHIFT;
|
|
tp->tm_mday = rtc_bcd2bin(tmp);
|
|
|
|
tmp = (dr & (RTC_DR_MU_MASK | RTC_DR_MT)) >> RTC_DR_MU_SHIFT;
|
|
tp->tm_mon = rtc_bcd2bin(tmp) - 1;
|
|
|
|
tmp = (dr & (RTC_DR_YU_MASK | RTC_DR_YT_MASK)) >> RTC_DR_YU_SHIFT;
|
|
tp->tm_year = rtc_bcd2bin(tmp) + 100;
|
|
|
|
#if defined(CONFIG_LIBC_LOCALTIME) || defined(CONFIG_TIME_EXTENDED)
|
|
tmp = (dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT;
|
|
tp->tm_wday = tmp % 7;
|
|
tp->tm_yday = tp->tm_mday + clock_daysbeforemonth(tp->tm_mon, clock_isleapyear(tp->tm_year + 1900));
|
|
tp->tm_isdst = 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
|
|
/* Return RTC sub-seconds if no configured and if a non-NULL value
|
|
* of nsec has been provided to receive the sub-second value.
|
|
*/
|
|
|
|
if (nsec)
|
|
{
|
|
uint32_t prediv_s;
|
|
uint32_t usecs;
|
|
|
|
prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK;
|
|
prediv_s >>= RTC_PRER_PREDIV_S_SHIFT;
|
|
|
|
ssr &= RTC_SSR_MASK;
|
|
|
|
/* Maximum prediv_s is 0x7fff, thus we can multiply by 100000 and
|
|
* still fit 32-bit unsigned integer.
|
|
*/
|
|
|
|
usecs = (((prediv_s - ssr) * 100000) / (prediv_s + 1)) * 10;
|
|
*nsec = usecs * 1000;
|
|
}
|
|
#endif /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */
|
|
|
|
rtc_dumptime((FAR const struct tm *)tp, "Returning");
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: up_rtc_getdatetime
|
|
*
|
|
* Description:
|
|
* Get the current date and time from the date/time RTC. This interface
|
|
* is only supported by the date/time RTC hardware implementation.
|
|
* It is used to replace the system timer. It is only used by the RTOS
|
|
* during initialization to set up the system time when CONFIG_RTC and
|
|
* CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not).
|
|
*
|
|
* NOTE: Some date/time RTC hardware is capability of sub-second accuracy.
|
|
* That sub-second accuracy is lost in this interface. However, since the
|
|
* system time is reinitialized on each power-up/reset, there will be no
|
|
* timing inaccuracy in the long run.
|
|
*
|
|
* Input Parameters:
|
|
* tp - The location to return the high resolution time value.
|
|
*
|
|
* Returned Value:
|
|
* Zero (OK) on success; a negated errno on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
|
|
int up_rtc_getdatetime(FAR struct tm *tp)
|
|
{
|
|
return stm32_rtc_getdatetime_with_subseconds(tp, NULL);
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_rtc_setdatetime
|
|
*
|
|
* Description:
|
|
* Set the RTC to the provided time. RTC implementations which provide
|
|
* up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide
|
|
* this function.
|
|
*
|
|
* Input Parameters:
|
|
* tp - the time to use
|
|
*
|
|
* Returned Value:
|
|
* Zero (OK) on success; a negated errno on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
int stm32_rtc_setdatetime(FAR const struct tm *tp)
|
|
{
|
|
uint32_t tr;
|
|
uint32_t dr;
|
|
int ret;
|
|
|
|
rtc_dumptime(tp, "Setting time");
|
|
|
|
/* Then write the broken out values to the RTC */
|
|
|
|
/* Convert the struct tm format to RTC time register fields. All of the STM32
|
|
* All of the ranges of values correspond between struct tm and the time
|
|
* register.
|
|
*/
|
|
|
|
tr = (rtc_bin2bcd(tp->tm_sec) << RTC_TR_SU_SHIFT) |
|
|
(rtc_bin2bcd(tp->tm_min) << RTC_TR_MNU_SHIFT) |
|
|
(rtc_bin2bcd(tp->tm_hour) << RTC_TR_HU_SHIFT);
|
|
|
|
/* Now convert the fields in struct tm format to the RTC date register
|
|
* fields:
|
|
*
|
|
* Days: 1-31 match in both cases.
|
|
* Month: STM32 is 1-12, struct tm is 0-11.
|
|
* Years: STM32 is 00-99, struct tm is years since 1900.
|
|
* WeekDay: STM32 is 1 = Mon - 7 = Sun
|
|
*
|
|
* Issue: I am not sure what the STM32 years mean. Are these the
|
|
* years 2000-2099? I'll assume so.
|
|
*/
|
|
|
|
dr = (rtc_bin2bcd(tp->tm_mday) << RTC_DR_DU_SHIFT) |
|
|
((rtc_bin2bcd(tp->tm_mon + 1)) << RTC_DR_MU_SHIFT) |
|
|
#if defined(CONFIG_LIBC_LOCALTIME) || defined(CONFIG_TIME_EXTENDED)
|
|
((tp->tm_wday == 0 ? 7 : (tp->tm_wday & 7)) << RTC_DR_WDU_SHIFT) |
|
|
#endif
|
|
((rtc_bin2bcd(tp->tm_year - 100)) << RTC_DR_YU_SHIFT);
|
|
|
|
dr &= ~RTC_DR_RESERVED_BITS;
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
|
|
rtc_wprunlock();
|
|
|
|
/* Set Initialization mode */
|
|
|
|
ret = rtc_enterinit();
|
|
if (ret == OK)
|
|
{
|
|
/* Set the RTC TR and DR registers */
|
|
|
|
putreg32(tr, STM32_RTC_TR);
|
|
putreg32(dr, STM32_RTC_DR);
|
|
|
|
/* Exit Initialization mode and wait for the RTC Time and Date
|
|
* registers to be synchronized with RTC APB clock.
|
|
*/
|
|
|
|
rtc_exitinit();
|
|
ret = rtc_synchwait();
|
|
}
|
|
|
|
/* Remember that the RTC is initialized and had its time set. */
|
|
|
|
if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET)
|
|
{
|
|
stm32_pwr_enablebkp(true);
|
|
putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG);
|
|
stm32_pwr_enablebkp(false);
|
|
}
|
|
|
|
/* Re-enable the write protection for RTC registers */
|
|
|
|
rtc_wprlock();
|
|
rtc_dumpregs("New time setting");
|
|
return ret;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: up_rtc_settime
|
|
*
|
|
* Description:
|
|
* Set the RTC to the provided time. All RTC implementations must be able
|
|
* to set their time based on a standard timespec.
|
|
*
|
|
* Input Parameters:
|
|
* tp - the time to use
|
|
*
|
|
* Returned Value:
|
|
* Zero (OK) on success; a negated errno on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
int up_rtc_settime(FAR const struct timespec *tp)
|
|
{
|
|
FAR struct tm newtime;
|
|
|
|
/* Break out the time values (not that the time is set only to units of
|
|
* seconds)
|
|
*/
|
|
|
|
(void)gmtime_r(&tp->tv_sec, &newtime);
|
|
return stm32_rtc_setdatetime(&newtime);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_rtc_setalarm
|
|
*
|
|
* Description:
|
|
* Set an alarm to an asbolute time using associated hardware.
|
|
*
|
|
* Input Parameters:
|
|
* alminfo - Information about the alarm configuration.
|
|
*
|
|
* Returned Value:
|
|
* Zero (OK) on success; a negated errno on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_RTC_ALARM
|
|
int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)
|
|
{
|
|
FAR struct alm_cbinfo_s *cbinfo;
|
|
rtc_alarmreg_t alarmreg;
|
|
int ret = -EINVAL;
|
|
|
|
ASSERT(alminfo != NULL);
|
|
DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id);
|
|
|
|
/* Make sure the the alarm interrupt is enabled at the NVIC */
|
|
|
|
rtc_enable_alarm();
|
|
|
|
/* REVISIT: Should test that the time is in the future */
|
|
|
|
rtc_dumptime(&alminfo->as_time, "New alarm time");
|
|
|
|
/* Break out the values to the HW alarm register format. The values in
|
|
* all STM32 fields match the fields of struct tm in this case. Notice
|
|
* that the alarm is limited to one month.
|
|
*/
|
|
|
|
alarmreg = (rtc_bin2bcd(alminfo->as_time.tm_sec) << RTC_ALRMR_SU_SHIFT) |
|
|
(rtc_bin2bcd(alminfo->as_time.tm_min) << RTC_ALRMR_MNU_SHIFT) |
|
|
(rtc_bin2bcd(alminfo->as_time.tm_hour) << RTC_ALRMR_HU_SHIFT) |
|
|
(rtc_bin2bcd(alminfo->as_time.tm_mday) << RTC_ALRMR_DU_SHIFT);
|
|
|
|
/* Set the alarm in hardware and enable interrupts from the RTC */
|
|
|
|
switch (alminfo->as_id)
|
|
{
|
|
case RTC_ALARMA:
|
|
{
|
|
cbinfo = &g_alarmcb[RTC_ALARMA];
|
|
cbinfo->ac_cb = alminfo->as_cb;
|
|
cbinfo->ac_arg = alminfo->as_arg;
|
|
|
|
ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE);
|
|
if (ret < 0)
|
|
{
|
|
cbinfo->ac_cb = NULL;
|
|
cbinfo->ac_arg = NULL;
|
|
}
|
|
|
|
rtc_dumpregs("Set AlarmA");
|
|
}
|
|
break;
|
|
|
|
#if CONFIG_RTC_NALARMS > 1
|
|
case RTC_ALARMB:
|
|
{
|
|
cbinfo = &g_alarmcb[RTC_ALARMB];
|
|
cbinfo->ac_cb = alminfo->as_cb;
|
|
cbinfo->ac_arg = alminfo->as_arg;
|
|
|
|
ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE);
|
|
if (ret < 0)
|
|
{
|
|
cbinfo->ac_cb = NULL;
|
|
cbinfo->ac_arg = NULL;
|
|
}
|
|
|
|
rtc_dumpregs("Set AlarmB");
|
|
}
|
|
break;
|
|
#endif
|
|
|
|
default:
|
|
rtcerr("ERROR: Invalid ALARM%d\n", alminfo->as_id);
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: stm32_rtc_cancelalarm
|
|
*
|
|
* Description:
|
|
* Cancel an alaram.
|
|
*
|
|
* Input Parameters:
|
|
* alarmid - Identifies the alarm to be cancelled
|
|
*
|
|
* Returned Value:
|
|
* Zero (OK) on success; a negated errno on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_RTC_ALARM
|
|
int stm32_rtc_cancelalarm(enum alm_id_e alarmid)
|
|
{
|
|
int ret = -EINVAL;
|
|
|
|
DEBUGASSERT(RTC_ALARM_LAST > alarmid);
|
|
|
|
/* Cancel the alarm in hardware and disable interrupts */
|
|
|
|
switch (alarmid)
|
|
{
|
|
case RTC_ALARMA:
|
|
{
|
|
/* Cancel the global callback function */
|
|
|
|
g_alarmcb[alarmid].ac_cb = NULL;
|
|
g_alarmcb[alarmid].ac_arg = NULL;
|
|
|
|
/* Need to follow RTC register wrote protection.
|
|
* Disable the write protection for RTC registers
|
|
*/
|
|
|
|
rtc_wprunlock();
|
|
|
|
/* Disable RTC alarm and interrupt */
|
|
|
|
modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0);
|
|
|
|
ret = rtchw_check_alrawf();
|
|
if (ret < 0)
|
|
{
|
|
goto errout_with_wprunlock;
|
|
}
|
|
|
|
/* Unset the alarm */
|
|
|
|
putreg32(-1, STM32_RTC_ALRMAR);
|
|
rtc_wprlock();
|
|
ret = OK;
|
|
}
|
|
break;
|
|
|
|
#if CONFIG_RTC_NALARMS > 1
|
|
case RTC_ALARMB:
|
|
{
|
|
/* Cancel the global callback function */
|
|
|
|
g_alarmcb[alarmid].ac_cb = NULL;
|
|
g_alarmcb[alarmid].ac_arg = NULL;
|
|
|
|
/* Need to follow RTC register wrote protection.
|
|
* Disable the write protection for RTC registers
|
|
*/
|
|
|
|
rtc_wprunlock();
|
|
|
|
/* Disable RTC alarm and interrupt */
|
|
|
|
modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0);
|
|
|
|
ret = rtchw_check_alrbwf();
|
|
if (ret < 0)
|
|
{
|
|
goto errout_with_wprunlock;
|
|
}
|
|
|
|
/* Unset the alarm */
|
|
|
|
putreg32(-1, STM32_RTC_ALRMBR);
|
|
rtc_wprlock();
|
|
ret = OK;
|
|
}
|
|
break;
|
|
#endif
|
|
|
|
default:
|
|
rtcerr("ERROR: Invalid ALARM%d\n", alarmid);
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
|
|
errout_with_wprunlock:
|
|
rtc_wprlock();
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
#endif /* CONFIG_RTC */
|