b6a6c21d01
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2627 42af7a65-404d-4744-a932-0658087f49c3
167 lines
8.2 KiB
C
Executable File
167 lines
8.2 KiB
C
Executable File
/****************************************************************************
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* drivers/net/enc28j60.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __DRIVERS_NET_ENC28J60_H
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#define __DRIVERS_NET_ENC28J60_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* A total of seven instructions are implemented on the ENC28J60 */
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#define ENC28J60_RCR (0x00) /* Read Control Register
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* 000 | aaaaa | (Registe value returned)) */
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#define ENC28J60_RBM (0x3a) /* Read Buffer Memory
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* 001 | 11010 | (Read buffer data follows) */
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#define ENC28J60_WCR (0x40) /* Write Control Register
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* 010 | aaaaa | dddddddd */
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#define ENC28J60_WBM (0x7a) /* Write Buffer Memory
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* 011 | 11010 | (Write buffer data follows) */
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#define ENC28J60_BFS (0x80) /* Bit Field Set
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* 100 | aaaaa | dddddddd */
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#define ENC28J60_BFC (0xa0) /* Bit Field Clear
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* 101 | aaaaa | dddddddd */
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#define ENC28J60_SRC (0xff) /* System Reset
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* 111 | 11111 | (No data) */
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/* Control registers are accessed with the RCR, RBM, WCR, BFS, and BFC commands.
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* The following identifies all ENC28J60 control registers. The Control register
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* memory is partitioned into four banks, selectable by the bank select bits,
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* BSEL1:BSEL0, in the ECON1 register.
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*
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* The last five locations (0x1b to 0x1f) of all banks point to a common set of
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* registers: EIE, EIR, ESTAT, ECON2 and ECON1. These are key registers used
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* in controlling and monitoring the operation of the device. Their common
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* mapping allows easy access without switching the bank.
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*
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* Control registers for the ENC28J60 are generically grouped as ETH, MAC and
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* MII registers. Register names starting with E belong to the ETH group. Similarly,
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* registers names starting with MA belong to the MAC group and registers prefixed
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* with MI belong to the MII group.
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*/
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#define EIE (0x1b) /* Ethernet Interrupt Enable Register */
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#define EIR (0x1c) /* Ethernet Interupt Request Register */
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#define ESTAT (0x1d) /* Ethernet Status Register */
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#define ECON2 (0x1e) /* Ethernet Control 2 Register */
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#define ECON1 (0x1f) /* Ethernet Control 1 Register */
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/* Ethernet Interrupt Enable Register Bit Definitions */
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#define EIE_RXERIE (1 << 0) /* Bit 0: Receive Error Interrupt Enable */
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#define EIE_TXERIE (1 << 1) /* Bit 1: Transmit Error Interrupt Enable */
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/* Bit 2: Reserved */
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#define EIE_TXIE (1 << 3) /* Bit 3: Transmit Enable */
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#define EIE_LINKIE (1 << 4) /* Bit 4: Link Status Change Interrupt Enable */
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#define EIE_DMAIE (1 << 5) /* Bit 5: DMA Interrupt Enable */
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#define EIE_PKTIE (1 << 6) /* Bit 6: Receive Packet Pending Interrupt Enable */
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#define EIE_INTIE (1 << 7) /* Bit 7: Global INT Interrupt Enable */
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/* Ethernet Interupt Request Register Bit Definitions */
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#define EIR_RXERIF (1 << 0) /* Bit 0: Receive Error Interrupt */
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#define EIR_TXERIF (1 << 1) /* Bit 1: Transmit Error Interrupt */
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/* Bit 2: Reserved */
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#define EIR_TXIF (1 << 3) /* Bit 3: Transmit Interrupt */
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#define EIR_LINKIF (1 << 4) /* Bit 4: Link Change Interrupt */
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#define EIR_DMAIF (1 << 5) /* Bit 5: DMA Interrupt */
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#define EIR_PKTIF (1 << 6) /* Bit 6: Receive Packet Pending Interrupt */
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/* Bit 7: Reserved */
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/* Ethernet Status Register Bit Definitions */
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#define ESTAT_CLKRDY (1 << 0) /* Bit 0: Clock Ready */
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#define ESTAT_TXABRT (1 << 1) /* Bit 1: Transmit Abort Error */
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#define ESTAT_RXBUSY (1 << 2) /* Bit 2: Receive Busy */
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/* Bit 3: Reserved */
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#define ESTAT_LATECOL (1 << 4) /* Bit 4: Late Collision Error */
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/* Bit 5: Reserved */
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#define ESTAT_BUFER (1 << 6) /* Bit 6: Ethernet Buffer Error Status */
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#define ESTAT_INT (1 << 7) /* Bit 7: INT Interrupt */
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/* Ethernet Control 1 Register Bit Definitions */
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#define ECON1_BSEL_SHIFT (0) /* Bits 0-1: Bank select */
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#define ECON1_BSEL_MASK (3 << ECON1_BSEL_SHIFT)
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# define ECON1_BSEL_BANK0 (0 << 0) /* Bank 0 */
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# define ECON1_BSEL_BANK1 (1 << 1) /* Bank 1 */
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# define ECON1_BSEL_BANK2 (2 << 0) /* Bank 2 */
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# define ECON1_BSEL_BANK3 (3 << 0) /* Bank 3 */
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#define ECON1_RXEN (1 << 2) /* Bit 2: Receive Enable */
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#define ECON1_TXRTS (1 << 3) /* Bit 3: Transmit Request to Send */
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#define ECON1_CSUMEN (1 << 4) /* Bit 4: DMA Checksum Enable */
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#define ECON1_DMAST (1 << 5) /* Bit 5: DMA Start and Busy Status */
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#define ECON1_RXRST (1 << 6) /* Bit 6: Receive Logic Reset */
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#define ECON1_TXRST (1 << 7) /* Bit 7: Transmit Logic Reset */
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/* Ethernet Control 2 Register */
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/* Bits 0-2: Reserved */
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#define ECON2_VRPS (1 << 3) /* Bit 3: Voltage Regulator Power Save Enable */
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/* Bit 4: Reserved */
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#define ECON2_PWRSV (1 << 5) /* Bit 5: Power Save Enable */
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#define ECON2_PKTDEC (1 << 6) /* Bit 6: Packet Decrement */
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#define ECON2_AUTOINC (1 << 7) /* Bit 7: Automatic Buffer Pointer Increment Enable */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DRIVERS_NET_ENC28J60_H */
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