246 lines
7.3 KiB
C
246 lines
7.3 KiB
C
/****************************************************************************
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* boards/arm/sam34/sam4s-xplained-pro/src/sam_nandflash.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/mtd/mtd.h>
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#include <nuttx/fs/fs.h>
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#include <nuttx/fs/nxffs.h>
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#include <arch/board/board.h>
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#include "arm_arch.h"
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#include "sam_periphclks.h"
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#include "sam4s_nand.h"
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#include "hardware/sam_smc.h"
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#include "hardware/sam4s_pinmap.h"
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#include "hardware/sam_matrix.h"
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#include "sam4s-xplained-pro.h"
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#ifdef HAVE_NAND
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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static const gpio_pinset_t g_nandpins[] =
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{
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GPIO_SMC_NCS0, GPIO_SMC_NANDALE, GPIO_SMC_NANDCLE,
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GPIO_SMC_NANDOE, GPIO_SMC_NANDWE, GPIO_SMC_RB,
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GPIO_SMC_D0, GPIO_SMC_D1, GPIO_SMC_D2, GPIO_SMC_D3,
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GPIO_SMC_D4, GPIO_SMC_D5, GPIO_SMC_D6, GPIO_SMC_D7
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};
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#define NAND_NPINS (sizeof(g_nandpins) / sizeof(gpio_pinset_t))
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: board_nandflash_config
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*
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* Description:
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* If CONFIG_SAM34_EXTNAND is defined, then NAND FLASH support is
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* enabled. This function provides the board-specific implementation of
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* the logic to reprogram the SMC to support NAND FLASH on the specified
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* CS.
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*
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* Input Parameters:
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* cs - Chip select number (in the event that multiple NAND devices
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* are connected on-board).
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*
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* Returned Value:
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* OK if the HSMC was successfully configured for this CS. A negated
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* errno value is returned on a failure. This would fail with -ENODEV,
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* for example, if the board does not support NAND FLASH on the requested
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* CS.
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*
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****************************************************************************/
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int board_nandflash_config(int cs)
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{
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/* The Embest and Ronetix CM boards and one Hynix NAND HY27UF(08/16)2G2B
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* Series NAND (MT29F2G08ABAEAWP).
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* This part has a capacity of 256Mx8bit () with spare 8Mx8 bit capacity.
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* The device contains 2048 blocks, composed by 64 x 2112 byte pages.
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* The effective size is approximately 256MiB.
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*
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* NAND is available on NCS0.
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*/
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int i;
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/* Configure GPIO pins (leaving SRAM in the disabled state) */
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for (i = 0; i < NAND_NPINS; i++)
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{
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sam_configgpio(g_nandpins[i]);
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}
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/* SMC NAND Flash Chip Select Configuration Register */
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putreg32(MATRIX_CCFG_SMCNFCS_SMC_NFCS(cs), SAM_MATRIX_CCFG_SMCNFCS);
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/* below from sam4s-xplained */
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sam_smc_enableclk();
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/* Configure SMC setup timing */
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putreg32(SMCCS_SETUP_NWESETUP(3) | SMCCS_SETUP_NCSWRSETUP(1) |
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SMCCS_SETUP_NRDSETUP(2) | SMCCS_SETUP_NCSRDSETUP(1),
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SAM_SMCCS_SETUP(cs));
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/* Configure the SMC pulse timing */
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putreg32(SMCCS_PULSE_NWEPULSE(5) | SMCCS_PULSE_NCSWRPULSE(5) |
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SMCCS_PULSE_NRDPULSE(5) | SMCCS_PULSE_NCSRDPULSE(5),
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SAM_SMCCS_PULSE(cs));
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/* Configure the SMC cycle timing */
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/**
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* Select 0. Chip Select 0 has been programmed with:
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* NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
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* NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
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* TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
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*/
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putreg32(SMCCS_CYCLE_NWECYCLE(12) | SMCCS_CYCLE_NRDCYCLE(11),
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SAM_SMCCS_CYCLE(cs));
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/* Configure the SMC mode */
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/**
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*
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* READ_MODE:
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* 0: The read operation is controlled by the NCS signal.
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* 1: The read operation is controlled by the NRD signal.
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*
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**/
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putreg32(SMCCS_MODE_TDFCYCLES(6) | SMCCS_MODE_TDFMODE |
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SMCCS_MODE_WRITEMODE | SMCCS_MODE_READMODE,
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SAM_SMCCS_MODE(cs));
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/* Configure NAND PIO pins
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*
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* NAND Interface NAND DESC
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*
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* NCS0 CE - Dedicated pin; no configuration needed
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* NANDCLE CLE - Dedicated pin; no configuration needed
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* NANDALE ALE - Dedicated pin; no configuration needed
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* NANDOE RE - Dedicated pin; no configuration needed
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* NANDWE WE - Dedicated pin; no configuration needed
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* NAND_RB RB - PC13
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* IO_D0-7 IO0-7 - Dedicated pins; no configuration needed
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*/
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sam_configgpio(GPIO_SMC_NANDALE);
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sam_configgpio(GPIO_SMC_NANDCLE);
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return OK;
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}
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/****************************************************************************
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* Name: sam_nand_automount
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*
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* Description:
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* Initialize and configure the NAND on CS3
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*
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****************************************************************************/
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int sam_nand_automount(int minor)
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{
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FAR struct mtd_dev_s *mtd;
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static bool initialized = false;
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/* Have we already initialized? */
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if (!initialized)
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{
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/* Create and initialize an NAND MATD device */
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mtd = sam_nand_initialize(SAM_SMC_CS0);
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if (!mtd)
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{
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ferr("ERROR: Failed to create the NAND driver on CS%d\n",
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SAM_SMC_CS0);
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return -ENODEV;
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}
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#if defined(CONFIG_SAM34_NAND_FTL)
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/* Use the FTL layer to wrap the MTD driver as a block driver */
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int ret = OK;
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ret = ftl_initialize(NAND_MINOR, mtd);
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if (ret < 0)
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{
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ferr("ERROR: Failed to initialize the FTL layer: %d\n", ret);
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return ret;
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}
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#elif defined(CONFIG_SAM34_NAND_NXFFS)
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/* Initialize to provide NXFFS on the MTD interface */
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int ret = OK;
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ret = nxffs_initialize(mtd);
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if (ret < 0)
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{
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ferr("ERROR: NXFFS initialization failed: %d\n", ret);
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return ret;
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}
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/* Mount the file system at /mnt/nand */
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ret = nx_mount(NULL, "/mnt/nand", "nxffs", 0, NULL);
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if (ret < 0)
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{
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ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret);
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return ret;
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}
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#endif
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/* Now we are initialized */
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initialized = true;
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}
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return OK;
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}
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#endif /* HAVE_NAND */
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