659 lines
19 KiB
C
659 lines
19 KiB
C
/****************************************************************************
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* arch/arm/src/samv7/sam_gpio.c
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* General Purpose Input/Output (GPIO) logic for the SAMV71
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*
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* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <time.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "sam_gpio.h"
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#include "hardware/sam_pio.h"
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#include "hardware/sam_matrix.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#if !defined(CONFIG_SAMV7_ERASE_ENABLE) || \
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!defined(CONFIG_SAMV7_JTAG_FULL_ENABLE)
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# if defined(CONFIG_SAMV7_ERASE_DISABLE)
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# define SYSIO_ERASE_BIT MATRIX_CCFG_SYSIO_SYSIO12
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# else
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# define SYSIO_ERASE_BIT 0
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# endif
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# if defined(CONFIG_SAMV7_JTAG_DISABLE)
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# define SYSIO_BITS (MATRIX_CCFG_SYSIO_SYSIO4 | MATRIX_CCFG_SYSIO_SYSIO5 | \
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MATRIX_CCFG_SYSIO_SYSIO6 | MATRIX_CCFG_SYSIO_SYSIO7)
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# endif
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# if defined(CONFIG_SAMV7_JTAG_FULL_SW_ENABLE)
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# define SYSIO_BITS MATRIX_CCFG_SYSIO_SYSIO4
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# endif
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# if defined(CONFIG_SAMV7_JTAG_SW_ENABLE)
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# define SYSIO_BITS (MATRIX_CCFG_SYSIO_SYSIO4 | MATRIX_CCFG_SYSIO_SYSIO5)
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# endif
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#endif
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#if !defined(SYSIO_BITS)
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# define SYSIO_BITS 0
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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#ifdef CONFIG_DEBUG_GPIO_INFO
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static const char g_portchar[SAMV7_NPIO] =
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{
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'A'
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#if SAMV7_NPIO > 1
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, 'B'
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#endif
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#if SAMV7_NPIO > 2
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, 'C'
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#endif
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#if SAMV7_NPIO > 3
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, 'D'
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#endif
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#if SAMV7_NPIO > 4
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, 'E'
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#endif
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};
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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const uintptr_t g_portbase[SAMV7_NPIO] =
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{
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SAM_PIOA_BASE
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#if SAMV7_NPIO > 1
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, SAM_PIOB_BASE
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#endif
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#if SAMV7_NPIO > 2
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, SAM_PIOC_BASE
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#endif
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#if SAMV7_NPIO > 3
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, SAM_PIOD_BASE
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#endif
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#if SAMV7_NPIO > 4
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, SAM_PIOE_BASE
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#endif
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: sam_configinput
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*
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* Description:
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* Configure a GPIO input pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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static inline int sam_configinput(uintptr_t base, uint32_t pin,
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gpio_pinset_t cfgset)
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{
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#ifdef GPIO_HAVE_SCHMITT
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uint32_t regval;
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#endif
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/* Disable interrupts on the pin */
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putreg32(pin, base + SAM_PIO_IDR_OFFSET);
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/* Enable/disable the pull-up as requested */
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if ((cfgset & GPIO_CFG_PULLUP) != 0)
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{
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#ifdef GPIO_HAVE_PULLDOWN
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/* The pull-up on a pin can not be enabled if its pull-down is still
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* active. Therefore, we need to disable the pull-down first before
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* enabling the pull-up.
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*/
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putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
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#endif
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putreg32(pin, base + SAM_PIO_PUER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
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}
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#ifdef GPIO_HAVE_PULLDOWN
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/* Enable/disable the pull-down as requested */
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if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
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{
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/* The pull-down on a pin can not be enabled if its pull-up is still
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* active. Therefore, we need to disable the pull-up first before
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* enabling the pull-down.
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*/
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putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
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putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
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}
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#endif
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/* Check if filtering should be enabled */
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if ((cfgset & GPIO_CFG_DEGLITCH) != 0)
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{
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putreg32(pin, base + SAM_PIO_IFER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_IFDR_OFFSET);
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}
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#ifdef GPIO_HAVE_SCHMITT
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/* Enable/disable the Schmitt trigger */
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regval = getreg32(base + SAM_PIO_SCHMITT_OFFSET);
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if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
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{
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regval |= pin;
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}
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else
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{
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regval &= ~pin;
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}
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putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET);
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#endif
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#ifdef GPIO_HAVE_DRIVER
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/* Reset output drive strength (PIO outputs only) */
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regval = getreg32(base + SAM_PIO_DRIVER_OFFSET);
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regval &= ~pin;
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putreg32(regval, base + SAM_PIO_DRIVER_OFFSET);
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#endif
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/* Configure the pin as an input and enable the GPIO function */
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putreg32(pin, base + SAM_PIO_ODR_OFFSET);
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putreg32(pin, base + SAM_PIO_PER_OFFSET);
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/* To-Do: If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and
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* IFDGSR registers. This would probably best be done with
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* another, new API... perhaps sam_configfilter()
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*/
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return OK;
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}
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/****************************************************************************
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* Name: sam_configoutput
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*
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* Description:
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* Configure a GPIO output pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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static inline int sam_configoutput(uintptr_t base, uint32_t pin,
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gpio_pinset_t cfgset)
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{
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#ifdef GPIO_HAVE_DRIVER
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uint32_t regval;
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#endif
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/* Disable interrupts on the pin */
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putreg32(pin, base + SAM_PIO_IDR_OFFSET);
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/* Enable/disable the pull-up as requested */
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if ((cfgset & GPIO_CFG_PULLUP) != 0)
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{
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#ifdef GPIO_HAVE_PULLDOWN
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/* The pull-up on a pin can not be enabled if its pull-down is still
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* active. Therefore, we need to disable the pull-down first before
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* enabling the pull-up.
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*/
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putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
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#endif
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putreg32(pin, base + SAM_PIO_PUER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
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}
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#ifdef GPIO_HAVE_PULLDOWN
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/* Enable/disable the pull-down as requested */
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if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
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{
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/* The pull-down on a pin can not be enabled if its pull-up is still
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* active. Therefore, we need to disable the pull-up first before
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* enabling the pull-down.
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*/
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putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
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putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
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}
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#endif
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/* Enable the open drain driver if requrested */
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if ((cfgset & GPIO_CFG_OPENDRAIN) != 0)
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{
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putreg32(pin, base + SAM_PIO_MDER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_MDDR_OFFSET);
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}
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/* Set default value */
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if ((cfgset & GPIO_OUTPUT_SET) != 0)
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{
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putreg32(pin, base + SAM_PIO_SODR_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_CODR_OFFSET);
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}
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#ifdef GPIO_HAVE_DRIVER
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/* Select the pin output drive strength */
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regval = getreg32(base + SAM_PIO_DRIVER_OFFSET);
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if ((cfgset & GPIO_OUTPUT_DRIVE) != GPIO_OUTPUT_LOW_DRIVE)
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{
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regval |= pin;
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}
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else
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{
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regval &= ~pin;
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}
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putreg32(regval, base + SAM_PIO_DRIVER_OFFSET);
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#endif
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/* Configure the pin as an output and enable the GPIO function */
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putreg32(pin, base + SAM_PIO_OER_OFFSET);
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putreg32(pin, base + SAM_PIO_PER_OFFSET);
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return OK;
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}
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/****************************************************************************
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* Name: sam_configperiph
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*
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* Description:
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* Configure a GPIO pin driven by a peripheral A or B signal based on
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* bit-encoded description of the pin.
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*
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****************************************************************************/
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static inline int sam_configperiph(uintptr_t base, uint32_t pin,
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gpio_pinset_t cfgset)
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{
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uint32_t regval;
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/* Disable interrupts on the pin */
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putreg32(pin, base + SAM_PIO_IDR_OFFSET);
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/* Enable/disable the pull-up as requested */
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if ((cfgset & GPIO_CFG_PULLUP) != 0)
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{
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#ifdef GPIO_HAVE_PULLDOWN
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/* The pull-up on a pin can not be enabled if its pull-down is still
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* active. Therefore, we need to disable the pull-down first before
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* enabling the pull-up.
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*/
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putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
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#endif
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putreg32(pin, base + SAM_PIO_PUER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
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}
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#ifdef GPIO_HAVE_PULLDOWN
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/* Enable/disable the pull-down as requested */
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if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
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{
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/* The pull-down on a pin can not be enabled if its pull-up is still
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* active. Therefore, we need to disable the pull-up first before
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* enabling the pull-down.
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*/
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putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
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putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
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}
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#endif
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#ifdef GPIO_HAVE_DRIVER
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/* Reset output drive strength (PIO outputs only) */
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regval = getreg32(base + SAM_PIO_DRIVER_OFFSET);
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regval &= ~pin;
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putreg32(regval, base + SAM_PIO_DRIVER_OFFSET);
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#endif
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#ifdef GPIO_HAVE_PERIPHCD
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/* Configure pin, depending upon the peripheral A, B, C or D
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*
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* PERIPHA: ABCDSR1[n] = 0 ABCDSR2[n] = 0
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* PERIPHB: ABCDSR1[n] = 1 ABCDSR2[n] = 0
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* PERIPHC: ABCDSR1[n] = 0 ABCDSR2[n] = 1
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* PERIPHD: ABCDSR1[n] = 1 ABCDSR2[n] = 1
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*/
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regval = getreg32(base + SAM_PIO_ABCDSR1_OFFSET);
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if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA ||
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(cfgset & GPIO_MODE_MASK) == GPIO_PERIPHC)
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{
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regval &= ~pin;
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}
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else
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{
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regval |= pin;
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}
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putreg32(regval, base + SAM_PIO_ABCDSR1_OFFSET);
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regval = getreg32(base + SAM_PIO_ABCDSR2_OFFSET);
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if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA ||
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(cfgset & GPIO_MODE_MASK) == GPIO_PERIPHB)
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{
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regval &= ~pin;
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}
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else
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{
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regval |= pin;
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}
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putreg32(regval, base + SAM_PIO_ABCDSR2_OFFSET);
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#else
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/* Configure pin, depending upon the peripheral A or B:
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*
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* PERIPHA: ABSR[n] = 0
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* PERIPHB: ABSR[n] = 1
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*/
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regval = getreg32(base + SAM_PIO_ABSR_OFFSET);
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if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA)
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{
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regval &= ~pin;
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}
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else
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{
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regval |= pin;
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}
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putreg32(regval, base + SAM_PIO_ABSR_OFFSET);
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#endif
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/* Disable PIO functionality */
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putreg32(pin, base + SAM_PIO_PDR_OFFSET);
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Function: sam_gpioinit
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*
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* Description:
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* Based on configuration within the .config file, it does:
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* - Configures the CCFG_SYSIO bits.
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*
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* Typically called from sam_start().
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*
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* Assumptions:
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* This function is called early in the initialization sequence so that
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* no mutual exlusion is necessary.
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*
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****************************************************************************/
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#if !defined(CONFIG_SAMV7_ERASE_ENABLE) || \
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!defined(CONFIG_SAMV7_JTAG_FULL_ENABLE)
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void sam_gpioinit(void)
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{
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uint32_t regval;
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regval = getreg32(SAM_MATRIX_CCFG_SYSIO);
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regval |= (SYSIO_ERASE_BIT | SYSIO_BITS);
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putreg32(regval, SAM_MATRIX_CCFG_SYSIO);
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}
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#endif
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/****************************************************************************
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* Name: sam_configgpio
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*
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* Description:
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* Configure a GPIO pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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int sam_configgpio(gpio_pinset_t cfgset)
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{
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uintptr_t base = sam_gpio_base(cfgset);
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uint32_t pin = sam_gpio_pinmask(cfgset);
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irqstate_t flags;
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int ret;
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/* Disable interrupts to prohibit re-entrance. */
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flags = enter_critical_section();
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/* Enable writing to GPIO registers */
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putreg32(PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
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/* Handle the pin configuration according to pin type */
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switch (cfgset & GPIO_MODE_MASK)
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{
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case GPIO_ALTERNATE:
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case GPIO_INPUT:
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ret = sam_configinput(base, pin, cfgset);
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break;
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case GPIO_OUTPUT:
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ret = sam_configoutput(base, pin, cfgset);
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break;
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case GPIO_PERIPHA:
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case GPIO_PERIPHB:
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#ifdef GPIO_HAVE_PERIPHCD
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case GPIO_PERIPHC:
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case GPIO_PERIPHD:
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#endif
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ret = sam_configperiph(base, pin, cfgset);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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/* Disable writing to GPIO registers */
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putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
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leave_critical_section(flags);
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return ret;
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}
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/****************************************************************************
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* Name: sam_gpiowrite
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*
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* Description:
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* Write one or zero to the selected GPIO pin
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*
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****************************************************************************/
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void sam_gpiowrite(gpio_pinset_t pinset, bool value)
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{
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uintptr_t base = sam_gpio_base(pinset);
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uint32_t pin = sam_gpio_pinmask(pinset);
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if (value)
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{
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putreg32(pin, base + SAM_PIO_SODR_OFFSET);
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}
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else
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{
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putreg32(pin, base + SAM_PIO_CODR_OFFSET);
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}
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}
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/****************************************************************************
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* Name: sam_gpioread
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*
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* Description:
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* Read one or zero from the selected GPIO pin
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*
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****************************************************************************/
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bool sam_gpioread(gpio_pinset_t pinset)
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{
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uintptr_t base = sam_gpio_base(pinset);
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uint32_t pin = sam_gpio_pinmask(pinset);
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uint32_t regval;
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|
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/* Always read the Pin Data Status Register. Otherwise an Open-Drain
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* Output pin will not be read back correctly.
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*/
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regval = getreg32(base + SAM_PIO_PDSR_OFFSET);
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return (regval & pin) != 0;
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}
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|
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/************************************************************************************
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* Function: sam_dumpgpio
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*
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* Description:
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* Dump all GPIO registers associated with the base address of the provided pinset.
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*
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************************************************************************************/
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|
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#ifdef CONFIG_DEBUG_GPIO_INFO
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int sam_dumpgpio(uint32_t pinset, const char *msg)
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{
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|
irqstate_t flags;
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uintptr_t base;
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unsigned int port;
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|
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/* Get the base address associated with the PIO port */
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|
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port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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base = SAM_PION_BASE(port);
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|
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/* The following requires exclusive access to the GPIO registers */
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|
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flags = enter_critical_section();
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|
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gpioinfo("PIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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gpioinfo(" PSR: %08x OSR: %08x IFSR: %08x ODSR: %08x\n",
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getreg32(base + SAM_PIO_PSR_OFFSET), getreg32(base + SAM_PIO_OSR_OFFSET),
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getreg32(base + SAM_PIO_IFSR_OFFSET), getreg32(base + SAM_PIO_ODSR_OFFSET));
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gpioinfo(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n",
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|
getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
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|
getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
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|
gpioinfo(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n",
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|
getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
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|
getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIO_PPDSR_OFFSET));
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|
gpioinfo(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
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|
getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
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|
getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
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|
gpioinfo(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n",
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|
getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
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|
getreg32(base + SAM_PIO_ELSR_OFFSET), getreg32(base + SAM_PIO_FELLSR_OFFSET));
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|
gpioinfo(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n",
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|
getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
|
|
getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
|
|
gpioinfo(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
|
|
getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
|
|
getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
|
|
gpioinfo("SCHMITT: %08x DRIVER:%08x\n",
|
|
getreg32(base + SAM_PIO_SCHMITT_OFFSET), getreg32(base + SAM_PIO_DRIVER_OFFSET));
|
|
gpioinfo(" KER: %08x KRCR: %08x KDR: %08x KIMR: %08x\n",
|
|
getreg32(base + SAM_PIO_KER_OFFSET), getreg32(base + SAM_PIO_KRCR_OFFSET),
|
|
getreg32(base + SAM_PIO_KDR_OFFSET), getreg32(base + SAM_PIO_KIMR_OFFSET));
|
|
gpioinfo(" KSR: %08x KKPR: %08x KKRR: %08x\n",
|
|
getreg32(base + SAM_PIO_KSR_OFFSET), getreg32(base + SAM_PIO_KKPR_OFFSET),
|
|
getreg32(base + SAM_PIO_KKRR_OFFSET));
|
|
gpioinfo(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
|
|
getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
|
|
getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
|
|
|
|
leave_critical_section(flags);
|
|
return OK;
|
|
}
|
|
#endif
|