2ac2ce55d2
regards to the data used by the ROM. Static alloaction sections should end at the begining of the ROM data. The rest of memory (End of ROM data --> End of DRAM) is added to the heap. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
80 lines
2.9 KiB
Plaintext
80 lines
2.9 KiB
Plaintext
/****************************************************************************
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* boards/xtensa/esp32/esp32-core/scripts/esp32.template.ld
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* ESP32 Linker Script Memory Layout
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*
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* This file describes the memory layout (memory blocks) as virtual
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* memory addresses.
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*
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* esp32.common.ld contains output sections to link compiler output
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* into these memory blocks.
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*
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* NOTE: That this is not the actual linker script but rather a "template"
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* for the elf32_out.ld script. This template script is passed through
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* the C preprocessor to include selected configuration options.
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*
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****************************************************************************/
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#include <nuttx/config.h>
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this
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* uses subtracted from the length of the various regions. The 'data access
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* port' dram/drom regions map to the same iram/irom regions but are
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* connected to the data port of the CPU and eg allow bytewise access.
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*/
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/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
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/* Even though the segment name is iram, it is actually mapped to flash.
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*
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* NOTE: (0x20 offset above is a convenience for the app binary image
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* generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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iram0_2_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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* Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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* the amount of RAM available.
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*
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* Note: The length of this section should be 0x50000, and this extra
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* DRAM is available in heap at runtime. However due to static ROM memory
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* usage at this 176KB mark, the additional static memory temporarily cannot
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* be used.
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*/
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dram0_0_seg (RW) : org = 0x3ffb0000 + CONFIG_ESP32_BT_RESERVE_DRAM,
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len = 0x2c200 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM - CONFIG_ESP32_BT_RESERVE_DRAM
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3f400020, len = 0x400000 - 0x20
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/* RTC fast memory (executable). Persists over deep sleep. */
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rtc_iram_seg(RWX) : org = 0x400c0000, len = 0x2000
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/* RTC slow memory (data accessible). Persists over deep sleep.
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* Start of RTC slow memory is reserved for ULP co-processor code + data,
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* if enabled.
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*/
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rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32_ULP_COPROC_RESERVE_MEM,
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len = 0x1000 - CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
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}
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/* Heap ends at top of dram0_0_seg */
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_eheap = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM;
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/* Module text area ends at top of dram0_0_seg */
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_emodtext = 0x400a0000;
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