436 lines
11 KiB
C
436 lines
11 KiB
C
/****************************************************************************
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* arch/arm/include/armv7-m/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H
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#define __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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#ifndef __ASSEMBLY__
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# include <nuttx/compiler.h>
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# include <arch/armv7-m/nvicpri.h>
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# include <stdint.h>
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#endif
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/* Included implementation-dependent register save structure layouts */
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#ifndef CONFIG_ARMV7M_LAZYFPU
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# include <arch/armv7-m/irq_cmnvector.h>
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#else
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# include <arch/armv7-m/irq_lazyfpu.h>
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#endif
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Configuration ************************************************************/
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/* If this is a kernel build, how many nested system calls should we
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* support?
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*/
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#ifndef CONFIG_SYS_NNEST
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# define CONFIG_SYS_NNEST 2
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#endif
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/* Alternate register names *************************************************/
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#define REG_A1 REG_R0
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#define REG_A2 REG_R1
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#define REG_A3 REG_R2
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#define REG_A4 REG_R3
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#define REG_V1 REG_R4
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#define REG_V2 REG_R5
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#define REG_V3 REG_R6
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#define REG_V4 REG_R7
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#define REG_V5 REG_R8
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#define REG_V6 REG_R9
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#define REG_V7 REG_R10
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#define REG_SB REG_R9
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#define REG_SL REG_R10
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#define REG_FP REG_R11
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#define REG_IP REG_R12
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#define REG_SP REG_R13
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#define REG_LR REG_R14
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#define REG_PC REG_R15
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/* The PIC register is usually R10. It can be R9 is stack checking is enabled
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* or if the user changes it with -mpic-register on the GCC command line.
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*/
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#define REG_PIC REG_R10
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* This structure represents the return state from a system call */
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#ifdef CONFIG_LIB_SYSCALL
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struct xcpt_syscall_s
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{
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uint32_t excreturn; /* The EXC_RETURN value */
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uint32_t sysreturn; /* The return PC */
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};
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#endif
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/* The following structure is included in the TCB and defines the complete
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* state of the thread.
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*/
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struct xcptcontext
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{
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/* The following function pointer is non-zero if there
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* are pending signals to be processed.
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*/
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FAR void *sigdeliver; /* Actual type is sig_deliver_t */
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/* These are saved copies of LR, PRIMASK, and xPSR used during
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* signal processing.
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*
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* REVISIT: Because there is only one copy of these save areas,
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* only a single signal handler can be active. This precludes
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* queuing of signal actions. As a result, signals received while
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* another signal handler is executing will be ignored!
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*/
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uint32_t saved_pc;
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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uint32_t saved_basepri;
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#else
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uint32_t saved_primask;
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#endif
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uint32_t saved_xpsr;
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#ifdef CONFIG_BUILD_PROTECTED
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uint32_t saved_lr;
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/* This is the saved address to use when returning from a user-space
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* signal handler.
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*/
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uint32_t sigreturn;
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#endif
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#ifdef CONFIG_LIB_SYSCALL
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/* The following array holds the return address and the exc_return value
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* needed to return from each nested system call.
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*/
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uint8_t nsyscalls;
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struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
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#endif
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/* Register save area */
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uint32_t regs[XCPTCONTEXT_REGS];
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};
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* Name: up_irq_save, up_irq_restore, and friends.
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*
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* NOTE: This function should never be called from application code and,
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* as a general rule unless you really know what you are doing, this
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* function should not be called directly from operation system code either:
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* Typically, the wrapper functions, enter_critical_section() and
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* leave_critical section(), are probably what you really want.
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*/
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/* Get/set the PRIMASK register */
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static inline uint8_t getprimask(void) inline_function;
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static inline uint8_t getprimask(void)
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{
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uint32_t primask;
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__asm__ __volatile__
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(
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"\tmrs %0, primask\n"
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: "=r" (primask)
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:
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: "memory");
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return (uint8_t)primask;
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}
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static inline void setprimask(uint32_t primask) inline_function;
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static inline void setprimask(uint32_t primask)
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{
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__asm__ __volatile__
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(
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"\tmsr primask, %0\n"
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:
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: "r" (primask)
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: "memory");
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}
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static inline void cpsie(void) inline_function;
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static inline void cpsie(void)
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{
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__asm__ __volatile__ ("\tcpsie i\n");
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}
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static inline void cpsid(void) inline_function;
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static inline void cpsid(void)
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{
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__asm__ __volatile__ ("\tcpsid i\n");
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}
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/* Get/set the BASEPRI register. The BASEPRI register defines the minimum
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* priority for exception processing. When BASEPRI is set to a nonzero
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* value, it prevents the activation of all exceptions with the same or
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* lower priority level as the BASEPRI value.
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*/
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static inline uint8_t getbasepri(void) inline_function;
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static inline uint8_t getbasepri(void)
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{
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uint32_t basepri;
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__asm__ __volatile__
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(
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"\tmrs %0, basepri\n"
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: "=r" (basepri)
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:
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: "memory");
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return (uint8_t)basepri;
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}
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static inline void setbasepri(uint32_t basepri) inline_function;
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static inline void setbasepri(uint32_t basepri)
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{
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__asm__ __volatile__
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(
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"\tmsr basepri, %0\n"
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:
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: "r" (basepri)
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: "memory");
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}
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#ifdef CONFIG_ARMV7M_BASEPRI_WAR /* Cortex-M7 r0p1 Errata 837070 Workaround */
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/* Set the BASEPRI register (possibly increasing the priority).
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*
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* This may be retaining or raising priority. Cortex-M7 r0p1 Errata
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* 837070 Workaround may be required if we are raising the priority.
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*/
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static inline void raisebasepri(uint32_t basepri) inline_function;
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static inline void raisebasepri(uint32_t basepri)
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{
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register uint32_t primask;
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/* 1. Retain the previous value of the PRIMASK register,
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* 2 Disable all interrupts via the PRIMASK register. NOTE: They
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* could possibly already be disabled.
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* 3. Set the BASEPRI register as requested (possibly increasing the
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* priority)
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* 4. Restore the original value of the PRIMASK register, probably re-
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* enabling interrupts. This avoids the possibly undesirable side-
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* effect of unconditionally re-enabling interrupts.
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*/
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__asm__ __volatile__
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(
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"\tmrs %0, primask\n"
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"\tcpsid i\n"
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"\tmsr basepri, %1\n"
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"\tmsr primask, %0\n"
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: "+r" (primask)
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: "r" (basepri)
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: "memory");
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}
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#else
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# define raisebasepri(b) setbasepri(b);
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#endif
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/* Disable IRQs */
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static inline void up_irq_disable(void) inline_function;
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static inline void up_irq_disable(void)
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{
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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/* Probably raising priority */
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raisebasepri(NVIC_SYSH_DISABLE_PRIORITY);
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#else
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__asm__ __volatile__ ("\tcpsid i\n");
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#endif
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}
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/* Save the current primask state & disable IRQs */
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static inline irqstate_t up_irq_save(void) inline_function;
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static inline irqstate_t up_irq_save(void)
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{
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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/* Probably raising priority */
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uint8_t basepri = getbasepri();
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raisebasepri(NVIC_SYSH_DISABLE_PRIORITY);
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return (irqstate_t)basepri;
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#else
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unsigned short primask;
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/* Return the current value of primask register and set
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* bit 0 of the primask register to disable interrupts
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*/
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__asm__ __volatile__
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(
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"\tmrs %0, primask\n"
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"\tcpsid i\n"
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: "=r" (primask)
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:
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: "memory");
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return primask;
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#endif
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}
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/* Enable IRQs */
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static inline void up_irq_enable(void) inline_function;
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static inline void up_irq_enable(void)
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{
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/* In this case, we are always retaining or lowering the priority value */
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setbasepri(NVIC_SYSH_PRIORITY_MIN);
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__asm__ __volatile__ ("\tcpsie i\n");
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}
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/* Restore saved primask state */
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static inline void up_irq_restore(irqstate_t flags) inline_function;
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static inline void up_irq_restore(irqstate_t flags)
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{
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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/* In this case, we are always retaining or lowering the priority value */
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setbasepri((uint32_t)flags);
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#else
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/* If bit 0 of the primask is 0, then we need to restore
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* interrupts.
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*/
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__asm__ __volatile__
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(
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"\ttst %0, #1\n"
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"\tbne.n 1f\n"
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"\tcpsie i\n"
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"1:\n"
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:
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: "r" (flags)
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: "memory");
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#endif
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}
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/* Get/set IPSR */
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static inline uint32_t getipsr(void) inline_function;
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static inline uint32_t getipsr(void)
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{
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uint32_t ipsr;
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__asm__ __volatile__
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(
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"\tmrs %0, ipsr\n"
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: "=r" (ipsr)
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:
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: "memory");
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return ipsr;
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}
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/* Get/set CONTROL */
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static inline uint32_t getcontrol(void) inline_function;
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static inline uint32_t getcontrol(void)
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{
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uint32_t control;
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__asm__ __volatile__
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(
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"\tmrs %0, control\n"
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: "=r" (control)
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:
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: "memory");
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return control;
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}
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static inline void setcontrol(uint32_t control) inline_function;
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static inline void setcontrol(uint32_t control)
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{
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__asm__ __volatile__
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(
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"\tmsr control, %0\n"
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:
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: "r" (control)
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: "memory");
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}
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H */
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