104 lines
4.0 KiB
C
104 lines
4.0 KiB
C
/****************************************************************************
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* arch/arm/src/lc823450/lc823450_i2c.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_LC823450_LC823450_I2C_H
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#define __ARCH_ARM_SRC_LC823450_LC823450_I2C_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/i2c/i2c_master.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Addresses *******************************************************/
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#define LC823450_I2C0_REGBASE 0x40089000
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#define LC823450_I2C1_REGBASE 0x4008A000
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#define I2CCTL (0x0)
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#define I2CSTR (0x4)
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#define I2CTXD (0x8)
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#define I2CRXD (0xC)
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#define I2CCKS (0x10)
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/* Register Bitfield Definitions ********************************************/
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/* Control register */
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#define I2C_CTL_SDAD (1 << 0) /* Bit 0: SDA data output */
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#define I2C_CTL_SCLD (1 << 1) /* Bit 1: SCL data output */
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#define I2C_CTL_BC (1 << 2) /* Bit 2: Control I2C Bus forcely */
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#define I2C_CTL_SCLR (1 << 3) /* Bit 3: Clear internal state */
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#define I2C_CTL_IREQEN (1 << 4) /* Bit 4: Interrupt enable */
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#define I2C_CTL_ACK (1 << 5) /* Bit 5: ACK bit output enable */
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#define I2C_CTL_ST (1 << 6) /* Bit 6: Generate Start/Stop condition */
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#define I2C_CTL_TRX (1 << 7) /* Bit 7: TX or RX enable */
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#define I2C_CTL_SRST (1 << 8) /* Bit 8: Reset all registers */
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#define I2C_CTL_BTRIG (1 << 12) /* Bit 12: Trigger starting byte transfer/receive */
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#define I2C_CTL_FMODE (1 << 15) /* Bit 15: Fast or Standard mode enable */
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/* Status register */
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#define I2C_STR_SDAB (1 << 0) /* Bit 0: Monitor SDA pin */
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#define I2C_STR_SCLB (1 << 1) /* Bit 1: Monitor SCL pin */
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#define I2C_STR_ACKD (1 << 5) /* Bit 5: ACK detection */
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#define I2C_STR_IREQ (1 << 6) /* Bit 6: Interrupt status */
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#define I2C_STR_BBSY (1 << 7) /* Bit 7: Bus busy */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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struct i2c_master_s *lc823450_i2cbus_initialize(int port);
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int lc823450_i2cbus_uninitialize(struct i2c_master_s *dev);
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void lc823450_i2cbus_changetimeout(struct i2c_master_s *dev,
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uint32_t timeoms);
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#if defined(__cplusplus)
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}
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#endif
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#undef EXTERN
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_LC823450_LC823450_I2C_H */
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