433 lines
14 KiB
C
433 lines
14 KiB
C
/****************************************************************************
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* arch/arm/src/phy62xx/irq.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include "nvic.h"
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#include "arm_internal.h"
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#include "jump_function.h"
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#include "bus_dev.h"
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/* #include "phy62xx_irq.h" */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Get a 32-bit version of the default priority */
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#define DEFPRIORITY32 \
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(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
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NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT)
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: phy62xx_dumpnvic
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*
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* Description:
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* Dump some interesting NVIC registers
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*
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****************************************************************************/
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#if defined(CONFIG_DEBUG_IRQ_INFO)
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static void phy62xx_dumpnvic(const char *msg, int irq)
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{
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irqstate_t flags;
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flags = enter_critical_section();
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irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
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irqinfo(" ISER: %08x ICER: %08x\n",
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getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
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irqinfo(" ISPR: %08x ICPR: %08x\n",
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getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
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irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
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getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
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getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
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irqinfo(" %08x %08x %08x %08x\n",
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getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
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getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
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irqinfo("SYSCON:\n");
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irqinfo(" CPUID: %08x\n",
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getreg32(ARMV6M_SYSCON_CPUID));
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irqinfo(" ICSR: %08x AIRCR: %08x\n",
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getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
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irqinfo(" SCR: %08x CCR: %08x\n",
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getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
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irqinfo(" SHPR2: %08x SHPR3: %08x\n",
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getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
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leave_critical_section(flags);
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}
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#else
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# define phy62xx_dumpnvic(msg, irq)
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#endif
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/****************************************************************************
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* Name: phy62xx_nmi, phy62xx_busfault, phy62xx_usagefault, phy62xx_pendsv,
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* phy62xx_dbgmonitor, phy62xx_pendsv, phy62xx_reserved
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*
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* Description:
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* Handlers for various exceptions. None are handled and all are fatal
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* error conditions. The only advantage these provided over the default
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* unexpected interrupt handler is that they provide a diagnostic output.
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_FEATURES
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static int phy62xx_nmi(int irq, void *context, void *arg)
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{
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up_irq_save();
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_err("PANIC!!! NMI received\n");
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PANIC();
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return 0;
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}
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static int phy62xx_pendsv(int irq, void *context, void *arg)
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{
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up_irq_save();
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_err("PANIC!!! PendSV received\n");
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PANIC();
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return 0;
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}
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static int phy62xx_reserved(int irq, void *context, void *arg)
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{
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up_irq_save();
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_err("PANIC!!! Reserved interrupt\n");
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PANIC();
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return 0;
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}
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#endif
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/****************************************************************************
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* Name: phy62xx_clrpend
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*
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* Description:
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* Clear a pending interrupt at the NVIC.
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*
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****************************************************************************/
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static inline void phy62xx_clrpend(int irq)
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{
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/* This will be called on each interrupt exit whether the interrupt can be
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* enambled or not. So this assertion is necessarily lame.
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*/
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DEBUGASSERT((unsigned)irq < NR_IRQS);
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/* Check for an external interrupt */
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if (irq >= PHY62XX_IRQ_EXTINT && irq < (PHY62XX_IRQ_EXTINT + 32))
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{
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/* Set the appropriate bit in the ISER register to enable the
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* interrupt
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*/
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putreg32((1 << (irq - PHY62XX_IRQ_EXTINT)), ARMV6M_NVIC_ICPR);
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}
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_irqinitialize
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****************************************************************************/
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extern void exception_phy(void);
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extern void exception_common(void);
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#define svc(code) asm volatile("svc %[immediate]"::[immediate]"I"(code))
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#define SVC_CALL_WR 0
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/* irqid 0~31 */
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int irq_priority(int irqid, uint8_t priority)
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{
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#if 0
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uint32_t val = (uint32_t)(priority << 6);
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int idx = (irqid) / 4;
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int idx_mod = irqid % 4;
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uint32_t regaddr = ARMV6M_NVIC_IPR(idx);
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uint32_t regval = getreg32(regaddr);
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regval &= ~(0xfful << (idx_mod * 8));
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regval |= (val << (idx_mod * 8));
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putreg32(regval, regaddr);
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#endif
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return 0;
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}
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#ifdef CONFIG_PHY6222_SDK
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void LL_IRQHandler1(void);
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#endif
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void TIM1_IRQHandler1(void);
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#ifdef CONFIG_PHY6222_SDK
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void TIM2_IRQHandler1(void);
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#endif
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#ifdef CONFIG_PHY6222_SDK
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void TIM3_IRQHandler1(void);
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#endif
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#ifdef CONFIG_PHY6222_SDK
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void TIM5_IRQHandler1(void);
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#endif
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void up_irqinitialize(void)
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{
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uint32_t regaddr;
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int i;
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/* Disable all interrupts */
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putreg32(0xffffffff, ARMV6M_NVIC_ICER);
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/* Set all interrupts (and exceptions) to the default priority */
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putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR2);
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putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR3);
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/* Now set all of the interrupt lines to the default priority */
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for (i = 0; i < 8; i++)
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{
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regaddr = ARMV6M_NVIC_IPR(i);
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putreg32(DEFPRIORITY32, regaddr);
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}
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/* register jump table irq handler */
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JUMP_FUNCTION(NMI_HANDLER) = (uint32_t)&exception_common;
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JUMP_FUNCTION(HARDFAULT_HANDLER) = (uint32_t)&exception_phy;
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JUMP_FUNCTION(SVC_HANDLER) = (uint32_t)&exception_common;
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JUMP_FUNCTION(PENDSV_HANDLER) = (uint32_t)&exception_common;
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JUMP_FUNCTION(SYSTICK_HANDLER) = (uint32_t)&exception_common;
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/* Vectors 16 - 47 external irq handler */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 0) = (unsigned)&exception_common, /* 16+0 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 1) = (unsigned)&exception_common, /* 16+1 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 2) = (unsigned)&exception_common, /* 16+2 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 3) = (unsigned)&exception_common, /* 16+3 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 4) = (unsigned)&exception_phy, /* 16+4 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 5) = (unsigned)&exception_common, /* 16+5 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 6) = (unsigned)&exception_common, /* 16+6 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 7) = (unsigned)&exception_common, /* 16+7 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 8) = (unsigned)&exception_common, /* 16+8 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 9) = (unsigned)&exception_common, /* 16+9 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 10) = (unsigned)&exception_common, /* 16+10 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 11) = (unsigned)&exception_phy, /* 16+11 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 12) = (unsigned)&exception_common, /* 16+12 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 13) = (unsigned)&exception_common, /* 16+13 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 14) = (unsigned)&exception_common, /* 16+14 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 15) = (unsigned)&exception_common, /* 16+15 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 16) = (unsigned)&exception_phy, /* 16+16 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 17) = (unsigned)&exception_common, /* 16+17 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 18) = (unsigned)&exception_phy, /* 16+18 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 19) = (unsigned)&exception_common, /* 16+19 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 20) = (unsigned)&exception_phy, /* 16+20 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 21) = (unsigned)&exception_phy, /* 16+21 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 22) = (unsigned)&exception_phy, /* 16+22 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 23) = (unsigned)&exception_phy, /* 16+23 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 24) = (unsigned)&exception_common, /* 16+24 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 25) = (unsigned)&exception_common, /* 16+25 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 26) = (unsigned)&exception_common, /* 16+26 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 27) = (unsigned)&exception_common, /* 16+27 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 28) = (unsigned)&exception_common, /* 16+28 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 29) = (unsigned)&exception_common, /* 16+29 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 30) = (unsigned)&exception_common, /* 16+30 */
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JUMP_FUNCTION(V0_IRQ_HANDLER + 31) = (unsigned)&exception_common, /* 16+31 */
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/* Attach the SVCall and Hard Fault exception handlers. The SVCall
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* exception is used for performing context switches; The Hard Fault
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* must also be caught because a SVCall may show up as a Hard Fault
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* under certain conditions.
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*/
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irq_attach(PHY62XX_IRQ_SVCALL, arm_svcall, NULL);
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irq_attach(PHY62XX_IRQ_HARDFAULT, arm_hardfault, NULL);
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/* Attach all other processor exceptions (except reset and sys tick) */
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#ifdef CONFIG_DEBUG_FEATURES
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irq_attach(PHY62XX_IRQ_NMI, phy62xx_nmi, NULL);
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irq_attach(PHY62XX_IRQ_PENDSV, phy62xx_pendsv, NULL);
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irq_attach(PHY62XX_IRQ_RESERVED, phy62xx_reserved, NULL);
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#endif
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phy62xx_dumpnvic("initial", NR_IRQS);
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/* Initialize logic to support a second level of interrupt decoding for
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* configured pin interrupts.
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*/
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#ifdef CONFIG_STM32F0L0G0_GPIOIRQ
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phy62xx_gpioirqinitialize();
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#endif
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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/* And finally, enable interrupts */
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#ifdef CONFIG_PHY6222_SDK
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irq_attach(PHY62XX_IRQ_BB_IRQn, (xcpt_t)LL_IRQHandler1, NULL);
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#endif
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irq_attach(PHY62XX_IRQ_TIM1_IRQn, (xcpt_t)TIM1_IRQHandler1, NULL);
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#ifdef CONFIG_PHY6222_SDK
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irq_attach(PHY62XX_IRQ_TIM2_IRQn, (xcpt_t)TIM2_IRQHandler1, NULL);
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#endif
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#ifdef CONFIG_PHY6222_SDK
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irq_attach(PHY62XX_IRQ_TIM3_IRQn, (xcpt_t)TIM3_IRQHandler1, NULL);
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#endif
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#ifdef CONFIG_PHY6222_SDK
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irq_attach(PHY62XX_IRQ_TIM5_IRQn, (xcpt_t)TIM5_IRQHandler1, NULL);
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#endif
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irq_priority((IRQn_Type)BB_IRQn, IRQ_PRIO_REALTIME);
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irq_priority((IRQn_Type)TIM1_IRQn, IRQ_PRIO_HIGH); /* ll_EVT */
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#ifdef CONFIG_PHY6222_SDK
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irq_priority((IRQn_Type)TIM2_IRQn, IRQ_PRIO_HIGH); /* OSAL_TICK */
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#endif
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irq_priority((IRQn_Type)TIM3_IRQn, IRQ_PRIO_APP); /* OSAL_TICK */
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irq_priority((IRQn_Type)TIM4_IRQn, IRQ_PRIO_HIGH); /* LL_EXA_ADV */
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NVIC_EnableIRQ((IRQn_Type)BB_IRQn);
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NVIC_EnableIRQ((IRQn_Type)TIM1_IRQn); /* ll_EVT */
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#ifdef CONFIG_PHY6222_SDK
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NVIC_EnableIRQ((IRQn_Type)TIM2_IRQn);
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#endif
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NVIC_EnableIRQ((IRQn_Type)TIM3_IRQn);
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#ifdef CONFIG_PHY6222_SDK
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NVIC_EnableIRQ((IRQn_Type)TIM5_IRQn);
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#endif
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/* NVIC_EnableIRQ((IRQn_Type)TIM4_IRQn); */
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/* svc(SVC_CALL_WR); */
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up_irq_enable();
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#endif
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}
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/****************************************************************************
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* Name: up_disable_irq
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*
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* Description:
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* Disable the IRQ specified by 'irq'
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*
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****************************************************************************/
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void up_disable_irq(int irq)
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{
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DEBUGASSERT((unsigned)irq < NR_IRQS);
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/* Check for an external interrupt */
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if (irq >= PHY62XX_IRQ_EXTINT && irq < (PHY62XX_IRQ_EXTINT + 32))
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{
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/* Set the appropriate bit in the ICER register to disable the
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* interrupt
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*/
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putreg32((1 << (irq - PHY62XX_IRQ_EXTINT)), ARMV6M_NVIC_ICER);
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}
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/* Handle processor exceptions. Only SysTick can be disabled */
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else if (irq == PHY62XX_IRQ_SYSTICK)
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{
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modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0);
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}
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phy62xx_dumpnvic("disable", irq);
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}
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/****************************************************************************
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* Name: up_enable_irq
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*
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* Description:
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* Enable the IRQ specified by 'irq'
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*
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****************************************************************************/
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void up_enable_irq(int irq)
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{
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/* This will be called on each interrupt exit whether the interrupt can be
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* enabled or not. So this assertion is necessarily lame.
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*/
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DEBUGASSERT((unsigned)irq < NR_IRQS);
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/* Check for external interrupt */
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if (irq >= PHY62XX_IRQ_EXTINT && irq < (PHY62XX_IRQ_EXTINT + 32))
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{
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/* Set the appropriate bit in the ISER register to enable the
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* interrupt
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*/
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putreg32((1 << (irq - PHY62XX_IRQ_EXTINT)), ARMV6M_NVIC_ISER);
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}
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/* Handle processor exceptions. Only SysTick can be disabled */
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else if (irq == PHY62XX_IRQ_SYSTICK)
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{
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modifyreg32(ARMV6M_SYSTICK_CSR, 0, SYSTICK_CSR_ENABLE);
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}
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phy62xx_dumpnvic("enable", irq);
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}
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/****************************************************************************
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* Name: arm_ack_irq
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*
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* Description:
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* Acknowledge the IRQ
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*
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****************************************************************************/
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void arm_ack_irq(int irq)
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{
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phy62xx_clrpend(irq);
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}
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