351 lines
18 KiB
C
351 lines
18 KiB
C
/****************************************************************************
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* arch/arm/src/cxd56xx/cxd56_powermgr.h
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*
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* Copyright 2018 Sony Semiconductor Solutions Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
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* the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_CXD56XX_POWERMGR_H
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#define __ARCH_ARM_SRC_CXD56XX_POWERMGR_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define CXD56_PM_SET_CPUID(wrd0, cpuid) ((((cpuid) & 0xF) << 28) |\
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((wrd0) & 0x0FFFFFFF))
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#define CXD56_PM_SET_PROTO(msg, proto) ((((proto) & 0xF) << 24) |\
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((msg) & 0xF0FFFFFF))
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#define CXD56_PM_FIFO_PROTO_PM (10)
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#define CXD56_PM_FIFO_MSG_ID_BOOT_INDE (0)
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#define CXD56_PM_FIFO_MSG_ID_FREQLOCK (1)
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#define CXD56_PM_FIFO_MSG_ID_CLK_CHG_START (2)
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#define CXD56_PM_FIFO_MSG_ID_CLK_CHG_END (3)
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#define CXD56_PM_FIFO_MSG_ID_GET_CLK (4)
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#define CXD56_PM_FIFO_MSG_ID_HOT_SLEEP (5)
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#define CXD56_PM_FIFO_MSG_ID_RESUME (6)
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#define CXD56_PM_SYS_CPU (0)
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#define CXD56_PM_SYS_APP (2)
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#define CXD56_PM_TASK_PRIO (200)
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#define CXD56_PM_TASK_STACKSIZE (1024)
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#define CXD56_PM_MESSAGE_PRIO (1)
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#define CXD56_PM_INTERNAL_MGS_CLK_CHG_START (0)
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#define CXD56_PM_INTERNAL_MGS_CLK_CHG_END (1)
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#define CXD56_PM_INTERNAL_MGS_HOT_SLEEP (2)
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#define CXD56_PM_CALLBACK_ID_CLK_CHG_START (0)
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#define CXD56_PM_CALLBACK_ID_CLK_CHG_END (1)
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#define CXD56_PM_CALLBACK_ID_HOT_SLEEP (2)
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#define CXD56_PM_CALLBACK_ID_HOT_BOOT (3)
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#define PM_CPUFREQLOCK_FLAG_INITIALIZED (0x8000)
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/* Data corresponding to a clock tree */
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/* Power DOMAIN */
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#define PM_DOMAIN_SELF_CPU (0x00000000ul)
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#define PM_DOMAIN_SYSIOP (0x20000000ul)
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#define PM_DOMAIN_HOSTIF (0x40000000ul)
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#define PM_DOMAIN_PMU (0x60000000ul)
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#define PM_DOMAIN_SCU (0x80000000ul)
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#define PM_DOMAIN_APP (0xA0000000ul)
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#define PM_DOMAIN_GPS (0xC0000000ul)
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#define PM_DOMAIN_MASK (0xE0000000ul)
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#define PM_DOMAIN_PLUS (0x20000000ul)
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/* Clock Tree Bit Data */
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/* SYSIOP */
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#define PM_CLOCK_SYS_CTRL_SEL_B (0x00010000ul) /**< 16*/
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#define PM_CLOCK_SYSPLL_DIV_B (0x00008000ul) /**< 15:CKSEL_ROOT.SWCTL_CLK_SEL_RFPLL1 */
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#define PM_CLOCK_SYS_CPU_SEL_B (0x00002000ul) /**< 13:CKSEL_ROOT.SWCTL_CLK_SEL */
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#define PM_CLOCK_SYS_CPU_DIV_B (0x00001000ul) /**< 12:CKDIV_CPU_DSP_BUS.CK_M0 */
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#define PM_CLOCK_SYS_AHB_DIV_B (0x00000800ul) /**< 11:CKDIV_CPU_DSP_BUS.CK_AHB */
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#define PM_CLOCK_SYS_APB_DIV_B (0x00000400ul) /**< 10:CKDIV_CPU_DSP_BUS.CK_APB */
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#define PM_CLOCK_SYS_COMIF_DIV_B (0x00000200ul) /**< 9;CKDIV_COM.CK_COM */
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#define PM_CLOCK_SYS_UART1_SEL_B (0x00000100ul) /**< 8:CKSEL_SYSIOP_SUB.SEL_UART1 */
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#define PM_CLOCK_SYS_SFC_DIV_B (0x00000080ul) /**< 7:CKDIV_CPU_DSP_BUS.SFC_HCLK_LOW */
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#define PM_CLOCK_PMU_RTC_PCLK_SEL_B (0x00000040ul) /**< 6:CKSEL_PMU.SEL_RTC_PCLK */
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/* HOSTIF */
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#define PM_CLOCK_HIF_SEL_B (0x00000040ul) /**< CKSEL_SYSIOP.SEL_HOST */
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#define PM_CLOCK_HIF_DIV_B (0x00000020ul) /**< CKDIV_HOSTIFC.CK_HOSTIFC */
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#define PM_CLOCK_HIF_SEL2_B (0x00000004ul) /**< CKSEL_SYSIOP.SEL_HOST2 */
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#define PM_CLOCK_HIF_UART0_SEL_B (0x00000002ul) /**< CKSEL_SYSIOP.SEL_UART0 */
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#define PM_CLOCK_HIF_I2C_SEL_B (0x00000001ul) /**< CKSEL_SYSIOP.SEL_I2CS */
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/* SCU */
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#define PM_CLOCK_SCU_XOSC_DIV_B (0x00000010ul) /**< CKSEL_SCU.SEL_SCU_XTAL */
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#define PM_CLOCK_SCU_SEL_B (0x00000004ul) /**< CKSEL_SCU.SEL_SCU */
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#define PM_CLOCK_SCU_32K_SEL_B (0x00000008ul) /**< CKSEL_SCU.SEL_SCU_32K */
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#define PM_CLOCK_SCU_HPADC_SEL_B (0x00000002ul) /**< CKDIV_SCU.SCU_U32KH */
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#define PM_CLOCK_SCU_LPADC_DIV_B (0x00000001ul) /**< CKDIV_SCU.SCU_U32KL */
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/* APP */
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#define PM_CLOCK_APP_SYSPLL_DIV_B (0x00004000ul) /**< APP_CKSEL.SWCTL_CLK_SEL_SP */
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#define PM_CLOCK_APP_CPU_SEL_B (0x00000400ul) /**< APP_CKSEL.SWCTL_CLK_SEL */
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#define PM_CLOCK_APP_AUD_MCLK_DIV_B (0x00000200ul) /**< APP_DIV.AU_MCLK */
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#define PM_CLOCK_APP_AUD_MCLK_SEL_B (0x00000100ul) /**< APP_CKSEL.AU_MCLK */
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#define PM_CLOCK_APP_AHB_GEAR_B (0x00000080ul) /**< GEAR_AHB */
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#define PM_CLOCK_APP_UART_GEAR_B (0x00000040ul) /**< GEAR_IMG_UART */
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#define PM_CLOCK_APP_SPI_GEAR_B (0x00000020ul) /**< GEAR_IMG_SPI */
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#define PM_CLOCK_APP_WSPI_GEAR_B (0x00000008ul) /**< GEAR_IMG_WSPI */
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#define PM_CLOCK_APP_SDIO_GEAR_B (0x00000004ul) /**< GEAR_PER_SDIO */
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#define PM_CLOCK_APP_USB_GEAR_B (0x00000002ul) /**< GEAR_PER_USB */
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#define PM_CLOCK_APP_VSYNC_GEAR_B (0x00000001ul) /**< GEAR_M_IMG_VENB/GEAR_N_IMG_VENB */
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#define PM_CLOCK_APP_VSYNC_GEAR_N (0x00020000ul) /**< GEAR_N_IMG_VENB */
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/* GPS */
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#define PM_CLOCK_GPS_PLL_SEL_B (0x00004000ul) /**< CKSEL_ROOT.SEL_RF_PLL_0 */
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#define PM_CLOCK_GPS_ACQ_SEL_B (0x00000200ul) /**< CKSEL_GNSS_BB.SEL_ACQ */
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#define PM_CLOCK_GPS_ITP_TRK_SEL_B (0x00000080ul) /**< CKDIV_ITP.ITP_TRK */
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#define PM_CLOCK_GPS_BB_MODE_SEL_B (0x00000400ul) /**< CKSEL_GNSS_BB.GNSS_MODE */
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#define PM_CLOCK_GPS_LOGGER_SEL_B (0x00000040ul) /**< CKSEL_GNSS_BB.SEL_LOG */
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#define PM_CLOCK_GPS_ITB_FFT_SEL_B (0x00000020ul) /**< CKSEL_GNSS_BB.SEL_ITB_FFT */
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#define PM_CLOCK_GPS_BB_SEL_B (0x00000100ul) /**< CKSEL_GNSS_BB.SEL_GNSS_BB */
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#define PM_CLOCK_GPS_PPS_SEL_B (0x00000004ul) /**< CKSEL_GNSS_BB.SEL_PPS */
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#define PM_CLOCK_GPS_CPU_DIV_B (0x00000002ul) /**< GNSS_DIV.CPU */
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#define PM_CLOCK_GPS_AHB_DIV_B (0x00000001ul) /**< GNSS_DIV.AHB */
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/* PMU */
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#define PM_CLOCK_PMU_SEL_B (0x00000004ul) /**< CKSEL_ROOT.PMU_SWCTL_CLK_SEL */
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#define PM_CLOCK_PMU_PWCTL_SEL_B (0x00000002ul) /**< CKSEL_ROOT.SWCTL_CLK_SEL_RO_RTC */
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#define PM_CLOCK_PMU_PWCTL_DIV_B (0x00000001ul) /**< CKDIV_PMU.PMUA */
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#define PM_CLOCK_DOMAIN_MASK ( PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B |\
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PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_CPU_DIV_B |\
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PM_CLOCK_SYS_AHB_DIV_B)
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/* Clock Tree Data */
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/* Target_id bit field */
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/* |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| */
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/* | Domain | Domain another bit field | */
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/****************************************************************************
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* Base Define
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*****************************************************************************/
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/* SYSIOP */
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#define PM_CLOCK_SYS_CTRL_SEL (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B)
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#define PM_CLOCK_SYSPLL_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B)
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#define PM_CLOCK_SYS_CPU_SEL (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B)
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#define PM_CLOCK_SYS_CPU_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_CPU_DIV_B)
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#define PM_CLOCK_SYS_AHB_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_CPU_DIV_B | PM_CLOCK_SYS_AHB_DIV_B)
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#define PM_CLOCK_SYS_APB_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_CPU_DIV_B | PM_CLOCK_SYS_AHB_DIV_B | PM_CLOCK_SYS_APB_DIV_B)
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#define PM_CLOCK_SYS_COMIF_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_COMIF_DIV_B)
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#define PM_CLOCK_SYS_UART1_SEL (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_COMIF_DIV_B | PM_CLOCK_SYS_UART1_SEL_B)
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#define PM_CLOCK_SYS_SFC_DIV (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_SFC_DIV_B)
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#define PM_CLOCK_PMU_RTC_PCLK_SEL (PM_DOMAIN_SYSIOP | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_SYS_CPU_DIV_B| PM_CLOCK_SYS_AHB_DIV_B | PM_CLOCK_SYS_APB_DIV_B | PM_CLOCK_PMU_RTC_PCLK_SEL_B)
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/* HOSTIF */
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#define PM_CLOCK_HIF_SEL (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B)
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#define PM_CLOCK_HIF_DIV (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B | PM_CLOCK_HIF_DIV_B)
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#define PM_CLOCK_HIF_SEL2 (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B | PM_CLOCK_HIF_DIV_B | PM_CLOCK_SCU_XOSC_DIV_B | PM_CLOCK_HIF_SEL2_B)
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#define PM_CLOCK_HIF_UART0_SEL (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B | PM_CLOCK_HIF_DIV_B | PM_CLOCK_SCU_XOSC_DIV_B | PM_CLOCK_HIF_SEL2_B | PM_CLOCK_HIF_UART0_SEL_B)
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#define PM_CLOCK_HIF_I2C_SEL (PM_DOMAIN_HOSTIF | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_HIF_SEL_B | PM_CLOCK_HIF_DIV_B | PM_CLOCK_SCU_XOSC_DIV_B | PM_CLOCK_HIF_SEL2_B | PM_CLOCK_HIF_I2C_SEL_B)
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/* SCU */
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#define PM_CLOCK_SCU_XOSC_DIV (PM_DOMAIN_SCU | PM_CLOCK_SCU_XOSC_DIV_B)
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#define PM_CLOCK_SCU_SEL (PM_DOMAIN_SCU | PM_CLOCK_SCU_XOSC_DIV_B | PM_CLOCK_SCU_32K_SEL_B | PM_CLOCK_SCU_SEL_B)
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#define PM_CLOCK_SCU_32K_SEL (PM_DOMAIN_SCU | PM_CLOCK_SCU_32K_SEL_B)
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#define PM_CLOCK_SCU_HPADC_SEL (PM_DOMAIN_SCU | PM_CLOCK_SCU_32K_SEL_B | PM_CLOCK_SCU_HPADC_SEL_B)
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#define PM_CLOCK_SCU_LPADC_DIV (PM_DOMAIN_SCU | PM_CLOCK_SCU_32K_SEL_B | PM_CLOCK_SCU_LPADC_DIV_B)
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/* APP */
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#define PM_CLOCK_APP_SYSPLL_DIV (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_APP_SYSPLL_DIV_B)
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#define PM_CLOCK_APP_SEL (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B)
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#define PM_CLOCK_APP_AUD_MCLK_DIV (PM_DOMAIN_APP | PM_CLOCK_APP_AUD_MCLK_DIV_B)
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#define PM_CLOCK_APP_AUD_MCLK_SEL (PM_DOMAIN_APP | PM_CLOCK_APP_AUD_MCLK_DIV_B | PM_CLOCK_APP_AUD_MCLK_SEL_B)
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#define PM_CLOCK_APP_AHB_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_AHB_GEAR_B)
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#define PM_CLOCK_APP_UART_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_UART_GEAR_B)
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#define PM_CLOCK_APP_SPI_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_SPI_GEAR_B)
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#define PM_CLOCK_APP_WSPI_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_WSPI_GEAR_B)
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#define PM_CLOCK_APP_SDIO_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_SDIO_GEAR_B)
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#define PM_CLOCK_APP_USB_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_USB_GEAR_B)
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#define PM_CLOCK_APP_VSYNC_GEAR (PM_DOMAIN_APP | PM_CLOCK_SYS_CTRL_SEL_B |PM_CLOCK_APP_SYSPLL_DIV_B | PM_CLOCK_APP_CPU_SEL_B | PM_CLOCK_APP_VSYNC_GEAR_B)
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#define PM_CLOCK_APP_VSYNC_N_GEAR (PM_DOMAIN_APP | PM_CLOCK_APP_VSYNC_GEAR_N)
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/* GPS */
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#define PM_CLOCK_GPS_PLL_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_GPS_PLL_SEL_B)
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#define PM_CLOCK_GPS_ACQ_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B | PM_CLOCK_GPS_ACQ_SEL_B)
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#define PM_CLOCK_GPS_ITP_TRK_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B | PM_CLOCK_GPS_ACQ_SEL_B | PM_CLOCK_GPS_ITP_TRK_SEL_B)
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#define PM_CLOCK_GPS_BB_MODE_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B)
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#define PM_CLOCK_GPS_LOGGER_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_LOGGER_SEL_B)
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#define PM_CLOCK_GPS_ITB_FFT_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B | PM_CLOCK_GPS_ITB_FFT_SEL_B)
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#define PM_CLOCK_GPS_BB_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B | PM_CLOCK_GPS_BB_SEL_B)
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#define PM_CLOCK_GPS_PPS_SEL (PM_DOMAIN_GPS | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_GPS_PLL_SEL_B | PM_CLOCK_GPS_BB_MODE_SEL_B | PM_CLOCK_GPS_PPS_SEL_B)
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#define PM_CLOCK_GPS_CPU_DIV (PM_DOMAIN_GPS | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_GPS_CPU_DIV_B)
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#define PM_CLOCK_GPS_AHB_DIV (PM_DOMAIN_GPS | PM_CLOCK_SYS_CTRL_SEL_B | PM_CLOCK_SYSPLL_DIV_B | PM_CLOCK_SYS_CPU_SEL_B | PM_CLOCK_GPS_CPU_DIV_B | PM_CLOCK_GPS_AHB_DIV_B)
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/* PMU */
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#define PM_CLOCK_PMU_SEL (PM_DOMAIN_PMU | PM_CLOCK_PMU_SEL_B)
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#define PM_CLOCK_PMU_PWCTL_SEL (PM_DOMAIN_PMU | PM_CLOCK_PMU_SEL_B | PM_CLOCK_PMU_PWCTL_SEL_B)
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#define PM_CLOCK_PMU_PWCTL_DIV (PM_DOMAIN_PMU | PM_CLOCK_PMU_SEL_B | PM_CLOCK_PMU_PWCTL_SEL_B | PM_CLOCK_PMU_PWCTL_DIV_B )
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/****************************************************************************
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* cxd56_pm_getclock & cxd56_pm_register_callback Interface Define
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*****************************************************************************/
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#define PM_CLOCK_SYS_CTRL PM_CLOCK_SYS_CTRL_SEL
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#define PM_CLOCK_SYSPLL PM_CLOCK_SYSPLL_DIV
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#define PM_CLOCK_SYS_CPU PM_CLOCK_SYS_CPU_DIV
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#define PM_CLOCK_SYS_AHB PM_CLOCK_SYS_AHB_DIV
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#define PM_CLOCK_SYS_APB PM_CLOCK_SYS_APB_DIV
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#define PM_CLOCK_SYS_COMIF PM_CLOCK_SYS_COMIF_DIV
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#define PM_CLOCK_SYS_UART1 PM_CLOCK_SYS_UART1_SEL
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#define PM_CLOCK_SYS_SFC PM_CLOCK_SYS_SFC_DIV
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#define PM_CLOCK_XOSC (PM_DOMAIN_SYSIOP | 0x00100000ul)
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#define PM_CLOCK_RCOSC (PM_DOMAIN_SYSIOP | 0x00200000ul)
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#define PM_CLOCK_RTC (PM_DOMAIN_SYSIOP | 0x00080000ul)
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#define PM_CLOCK_PMU_I2C PM_CLOCK_PMU_RTC_PCLK_SEL
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/* HOSTIF */
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#define PM_CLOCK_HIF PM_CLOCK_HIF_SEL2
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#define PM_CLOCK_HIF_UART0 PM_CLOCK_HIF_UART0_SEL
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#define PM_CLOCK_HIF_I2C PM_CLOCK_HIF_I2C_SEL
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/* SCU */
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#define PM_CLOCK_SCU_XOSC PM_CLOCK_SCU_XOSC_DIV
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#define PM_CLOCK_SCU PM_CLOCK_SCU_SEL
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#define PM_CLOCK_SCU_32K PM_CLOCK_SCU_32K_SEL
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#define PM_CLOCK_SCU_HPADC PM_CLOCK_SCU_HPADC_SEL
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#define PM_CLOCK_SCU_LPADC PM_CLOCK_SCU_LPADC_DIV
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/* APP */
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#define PM_CLOCK_APP_SYSPLL PM_CLOCK_APP_SYSPLL_DIV
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#define PM_CLOCK_APP PM_CLOCK_APP_SEL
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#define PM_CLOCK_APP_AUD PM_CLOCK_APP_AUD_MCLK_SEL
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#define PM_CLOCK_APP_AHB PM_CLOCK_APP_AHB_GEAR
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#define PM_CLOCK_APP_CPU PM_CLOCK_APP_AHB
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#define PM_CLOCK_APP_UART PM_CLOCK_APP_UART_GEAR
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#define PM_CLOCK_APP_SPI PM_CLOCK_APP_SPI_GEAR
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#define PM_CLOCK_APP_WSPI PM_CLOCK_APP_WSPI_GEAR
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#define PM_CLOCK_APP_SDIO PM_CLOCK_APP_SDIO_GEAR
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#define PM_CLOCK_APP_USB PM_CLOCK_APP_USB_GEAR
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#define PM_CLOCK_APP_VSYNC PM_CLOCK_APP_VSYNC_GEAR
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#define PM_CLOCK_APP_VSYNC_N PM_CLOCK_APP_VSYNC_N_GEAR
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#define PM_CLOCK_APP_VSYNC_M PM_CLOCK_APP_VSYNC_GEAR
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/* GPS */
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#define PM_CLOCK_GPS_PLL PM_CLOCK_GPS_PLL_SEL
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#define PM_CLOCK_GPS_ACQ PM_CLOCK_GPS_ACQ_SEL
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#define PM_CLOCK_GPS_ITP_TRK PM_CLOCK_GPS_ITP_TRK_SEL
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#define PM_CLOCK_GPS_BB_MODE PM_CLOCK_GPS_BB_MODE_SEL
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#define PM_CLOCK_GPS_LOGGER PM_CLOCK_GPS_LOGGER_SEL
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#define PM_CLOCK_GPS_ITB_FFT PM_CLOCK_GPS_ITB_FFT_SEL
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#define PM_CLOCK_GPS_BB PM_CLOCK_GPS_BB_SEL
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#define PM_CLOCK_GPS_PPS PM_CLOCK_GPS_PPS_SEL
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#define PM_CLOCK_GPS_CPU PM_CLOCK_GPS_CPU_DIV
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#define PM_CLOCK_GPS_AHB PM_CLOCK_GPS_AHB_DIV
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/* PMU */
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#define PM_CLOCK_PMU PM_CLOCK_PMU_PWCTL_SEL
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#define PM_CLOCK_PMUA PM_CLOCK_PMU_PWCTL_DIV
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#define PM_CLOCK_SYS_DMAC PM_CLOCK_SYS_AHB
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#define PM_CLOCK_SYS_SAKE PM_CLOCK_SYS_AHB
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#define PM_CLOCK_SYS_KAKI PM_CLOCK_SYS_AHB
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#define PM_CLOCK_SYS_SPIM PM_CLOCK_SYS_COMIF
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#define PM_CLOCK_SYS_I2CM PM_CLOCK_SYS_COMIF
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#define PM_CLOCK_APP_DMAC PM_CLOCK_APP_AHB_GEAR
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#define PM_CLOCK_APP_SAKE PM_CLOCK_APP_AHB_GEAR
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#define PM_CLOCK_APP_KAKI PM_CLOCK_APP_AHB_GEAR
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#define PM_CLOCK_CPUID(id) ((0 == (id)) ? PM_CLOCK_SYS_CPU : \
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(1 == (id)) ? PM_CLOCK_GPS_CPU : \
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PM_CLOCK_APP_CPU)
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/* CPU status change callback */
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#define PM_CPU_STATUS_CHANGE (PM_DOMAIN_SELF_CPU | 0x10000000ul)
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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typedef int (*cxd56_pm_callback)(uint8_t id);
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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void *cxd56_pm_register_callback(uint32_t target, cxd56_pm_callback callback);
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void cxd56_pm_unregister_callback(void *handle);
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int cxd56_pm_fifo_handlear(int cpuid, uint32_t data[2]);
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int cxd56_pm_main_task(int argc, FAR char *argv[]);
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int cxd56_pm_initialize(void);
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int cxd56_pm_bootup(void);
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uint32_t cxd56_pm_getclock(uint32_t target);
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int cxd56_pm_hotsleep(int idletime);
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY */
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#endif /* __ARCH_ARM_SRC_CXD56XX_POWERMGR_H */
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