131 lines
4.5 KiB
ArmAsm
131 lines
4.5 KiB
ArmAsm
/****************************************************************************
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* arch/xtensa/src/common/xtensa_cpuint.S
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*
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* Adapted from use in NuttX by:
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Derives from logic originally provided by Cadence Design Systems Inc.
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*
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* Copyright (c) 2006-2015 Cadence Design Systems Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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****************************************************************************/
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.file "xtensa_cpuint.S"
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/chip/core-isa.h>
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#include <arch/xtensa/xtensa_abi.h>
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#if XCHAL_HAVE_INTERRUPTS
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: xtensa_enable_cpuint
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*
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* C Prototype:
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* uint32_t xtensa_enable_cpuint(uint32_t *shadow, unsigned int intmask)
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*
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* Description:
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* Enables a set of interrupts. Does not simply set INTENABLE directly,
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* but operates on a shadow copy of the CPU INTENABLE register then
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* writes that value to the hardware INTENABLE register. Can be called
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* from interrupt handlers.
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*
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* NOTE: It is possible only to enable interrupts on the current CPU
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* because there is an INTENABLE register implemented in each CPU.
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*
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****************************************************************************/
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.text
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.global xtensa_enable_cpuint
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.type xtensa_enable_cpuint, @function
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.align 4
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xtensa_enable_cpuint:
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ENTRY(16)
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movi a4, 0
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xsr a4, INTENABLE /* Disables all interrupts */
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rsync
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l32i a4, a2, 0 /* a4 = value of INTENABLE shadow */
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or a5, a4, a3 /* a5 = shadow | mask */
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s32i a5, a2, 0 /* shadow |= mask */
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wsr a5, INTENABLE /* Set CPU INTENABLE to shadow */
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mov a3, a4 /* Return previous shadow content */
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RET(16)
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.size xtensa_enable_cpuint, . - xtensa_enable_cpuint
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/****************************************************************************
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* Name: xtensa_disable_cpuint
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*
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* C Prototype:
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* uint32_t xtensa_disable_cpuint(uint32_t *shadow, unsigned int intmask)
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*
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* Description:
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* Disables a set of interrupts. Does not simply set INTENABLE directly,
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* but operates on a shadow copy of the CPU INTENABLE register then
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* writes that value to the hardware INTENABLE register. Can be called
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* from interrupt handlers.
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*
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* NOTE: It is possible only to disable interrupts on the current CPU
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* because there is an INTENABLE register implemented in each CPU.
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*
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****************************************************************************/
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.text
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.global xtensa_disable_cpuint
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.type xtensa_disable_cpuint, @function
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.align 4
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xtensa_disable_cpuint:
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ENTRY(16)
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movi a4, 0
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xsr a4, INTENABLE /* Disables all interrupts */
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rsync
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l32i a4, a2, 0 /* a4 = value of INTENABLE shadow */
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or a5, a4, a3 /* a5 = shadow | mask */
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xor a5, a5, a3 /* a5 = shadow & ~mask */
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s32i a5, a2, 0 /* shadow &= ~mask */
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wsr a5, INTENABLE /* Set CPU INTENABLE to shadow */
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mov a3, a4 /* Return previous shadow content */
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RET(16)
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.size xtensa_disable_cpuint, . - xtensa_disable_cpuint
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#endif /* XCHAL_HAVE_INTERRUPTS */
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