1000 lines
28 KiB
C
1000 lines
28 KiB
C
/************************************************************************************
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* arch/arm/src/armv7-r/cp15_cacheops.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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*
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* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright ©
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* 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.c (ID051414)
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*
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* Portions of this file derive from Atmel sample code for the SAMA5D3 Cortex-A5
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* which also has a modified BSD-style license:
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*
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* Copyright (c) 2012, Atmel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
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* be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV7_R_CP15_CACHEOPS_H
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#define __ARCH_ARM_SRC_ARMV7_R_CP15_CACHEOPS_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Cache definitions ****************************************************************/
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/* L1 Memory */
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#define CP15_L1_LINESIZE 32
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/* CP15 Registers *******************************************************************/
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/* Terms:
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* 1) Point of coherency (PoC)
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* The PoC is the point at which all agents that can access memory are guaranteed
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* to see the same copy of a memory location
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* 2) Point of unification (PoU)
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* The PoU is the point by which the instruction and data caches and the
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* translation table walks of the processor are guaranteed to see the same copy
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* of a memory location.
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*
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* Cache Operations:
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*
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* CP15 Register: ICIALLUIS
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* Description: Invalidate entire instruction cache Inner Shareable.
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* Register Format: Should be zero (SBZ)
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* Instruction: MCR p15, 0, <Rd>, c7, c1, 0
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* CP15 Register: BPIALLIS
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* Description: Invalidate entire branch predictor array Inner Shareable.
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* Register Format: Should be zero (SBZ)
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* Instruction: MCR p15, 0, <Rd>, c7, c1, 6
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* CP15 Register: ICIALLU
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* Description: Invalidate all instruction caches to PoU. Also flushes branch
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* target cache.
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* Register Format: Should be zero (SBZ)
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* Instruction: MCR p15, 0, <Rd>, c7, c5, 0
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* CP15 Register: ICIMVAU
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* Description: Invalidate instruction cache by VA to PoU.
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* Register Format: VA
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* Instruction: MCR p15, 0, <Rd>, c7, c5, 1
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* CP15 Register: CP15ISB
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* Description: Instruction Synchronization Barrier operation
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* NOTE: Deprecated and no longer documented
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* Instruction: MCR p15, 0, <Rd>, c7, c5, 4
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* CP15 Register: BPIALL
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* Description: Invalidate entire branch predictor array.
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* Register Format: Should be zero (SBZ)
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* Instruction: MCR p15, 0, <Rd>, c7, c5, 6
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* CP15 Register: BPIMVA
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* Description: Invalidate VA from branch predictor array.
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* Register Format: Should be zero (SBZ)
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* Instruction: MCR p15, 0, <Rd>, c7, c5, 7
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* CP15 Register: DCIMVAC
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* Description: Invalidate data cache line by VA to PoC.
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* Register Format: VA
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* Instruction: MCR p15, 0, <Rd>, c7, c6, 1
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* CP15 Register: DCISW
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* Description: Invalidate data cache line by Set/Way.
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* Register Format: Set/Way
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* Instruction: MCR p15, 0, <Rd>, c7, c6, 2
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* CP15 Register: DCCMVAC
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* Description: Clean data cache line to PoC by VA.
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* Register Format: VA
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* Instruction: MCR p15, 0, <Rd>, c7, c10, 1
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* CP15 Register: DCCSW
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* Description: Clean data cache line by Set/Way.
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* Register Format: Set/Way
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* Instruction: MCR p15, 0, <Rd>, c7, c10, 2
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* CP15 Register: CP15DSB
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* Description: Data Synchronization Barrier operation
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* NOTE: Deprecated and no longer documented
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* Instruction: MCR p15, 0, <Rd>, c7, c10, 4
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* CP15 Register: CP15DMB
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* Description: Data Memory Barrier operation
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* NOTE: Deprecated and no longer documented
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* Instruction: MCR p15, 0, <Rd>, c7, c10, 5
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* CP15 Register: DCCMVAU
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* Description: Clean data or unified cache line by VA to PoU.
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* Register Format: VA
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* Instruction: MCR p15, 0, <Rd>, c7, c11, 1
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* CP15 Register: DCCIMVAC
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* Description: Clean and invalidate data cache line by VA to PoC.
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* Register Format: VA
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* Instruction: MCR p15, 0, <Rd>, c7, c14, 1
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* CP15 Register: DCCISW
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* Description: Clean and invalidate data cache line by Set/Way.
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* Register Format: Set/Way
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* Instruction: MCR p15, 0, <Rd>, c7, c14, 2
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*/
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/* Set/way format */
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#define CACHE_WAY_SHIFT (3) /* Bits 30-31: Way in set being accessed */
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#define CACHE_WAY_MASK (3 << CACHE_WAY_SHIFT)
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#define CACHE_SET_SHIFT (5) /* Bits 5-(S+4): Way in set being accessed */
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/* For 4KB cache size: S=5 */
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#define CACHE_SET4KB_MASK (0x1f << CACHE_SET_SHIFT)
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/* Bits 10-29: Reserved */
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/* For 8KB cache size: S=6 */
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#define CACHE_SET8KB_MASK (0x3f << CACHE_SET_SHIFT)
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/* Bits 11-29: Reserved */
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/* For 16KB cache size: S=7 */
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#define CACHE_SET16KB_MASK (0x7f << CACHE_SET_SHIFT)
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/* Bits 12-29: Reserved */
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/* For 32KB cache size: S=8 */
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#define CACHE_SET32KB_MASK (0xff << CACHE_SET_SHIFT)
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/* Bits 13-29: Reserved */
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/* For 64KB cache size: S=9 */
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#define CACHE_SET64KB_MASK (0x1fff << CACHE_SET_SHIFT)
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/* Bits 14-29: Reserved */
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/* VA and SBZ format */
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#define CACHE_SBZ_SHIFT (4) /* Bits 0-4: Should be zero (SBZ) */
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#define CACHE_SBZ_MASK (31 << TLB_SBZ_SHIFT)
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#define CACHE_VA_MASK (0xfffffffe0) /* Bits 5-31: Virtual address */
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/************************************************************************************
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* Assemby Macros
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************************************************************************************/
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/* cp15_cache Cache Operations
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*
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* Usage
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*
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* They are performed as MCR instructions and only operate on a level 1 cache
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* associated with ARM v7 processor.
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*
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* The supported operations are:
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*
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* 1. Any of these operations can be applied to any data cache or any
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* unified cache.
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* 2. Invalidate by MVA. Performs an invalidate of a data or unified cache
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* line
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* based on the address it contains.
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* 3. Invalidate by set/way. Performs an invalidate of a data or unified
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* cache line based on its location in the cache hierarchy.
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* 4. Clean by MVA. Performs a clean of a data or unified cache line based
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* on the address it contains.
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* 5. Clean by set/way. Performs a clean of a data or unified cache line
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* based on its location in the cache hierarchy.
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* 6. Clean and Invalidate by MVA. Performs a clean and invalidate of a
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* data or unified cache line based on the address it contains.
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* 7. Clean and Invalidate by set/way. Performs a clean and invalidate of
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* a data or unified cache line based on its location in the cache
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* hierarchy.
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*
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* NOTE: Many of these operations are implemented as assembly language
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* macros or as C inline functions in the file cache.h. The larger functions
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* are implemented here as C-callable functions.
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*/
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#ifdef __ASSEMBLY__
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/************************************************************************************
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* Name: cp15_disable_dcache
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*
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* Description:
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* Disable L1 D Cache
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_disable_dcache, tmp
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mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
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bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */
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mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
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.endm
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/************************************************************************************
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* Name: cp15_disable_caches
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*
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* Description:
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* Disable L1 Caches
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_disable_caches, tmp
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mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */
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bic \tmp, \tmp, #(0x1 << 12) /* Disable I cache */
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bic \tmp, \tmp, #(0x1 << 2) /* Disable D cache */
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mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */
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.endm
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/************************************************************************************
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* Name: cp15_invalidate_icache_inner_sharable
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*
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* Description:
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* Invalidate I cache predictor array inner sharable
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_invalidate_icache_inner_sharable, tmp
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mov \tmp, #0
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mrc p15, 0, \tmp, c7, c1, 0 /* ICIALLUIS */
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.endm
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/************************************************************************************
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* Name: cp15_invalidate_btb_inner_sharable
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*
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* Description:
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* Invalidate entire branch predictor array inner sharable
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_invalidate_btb_inner_sharable, tmp
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mov \tmp, #0
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mrc p15, 0, \tmp, c7, c1, 6 /* BPIALLIS */
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.endm
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/************************************************************************************
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* Name: cp15_invalidate_icache
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*
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* Description:
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* Invalidate all instruction caches to PoU, also flushes branch target cache
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_invalidate_icache, tmp
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mov \tmp, #0
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mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */
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.endm
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/************************************************************************************
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* Name: cp15_invalidate_icache_bymva
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*
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* Description:
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* Invalidate instruction caches by VA to PoU
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*
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* Input Parameters:
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* va - Register with VA format
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_invalidate_icache_bymva, va
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mrc p15, 0, \va, c7, c5, 1 /* ICIMVAU */
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.endm
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/************************************************************************************
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* Name: cp15_flush_btb
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*
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* Description:
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* Invalidate entire branch predictor array
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_flush_btb, tmp
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mov \tmp, #0
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mrc p15, 0, \tmp, c7, c5, 6 /* BPIALL */
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.endm
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/************************************************************************************
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* Name: cp15_flush_btb_bymva
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*
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* Description:
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* Invalidate branch predictor array entry by MVA
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_flush_btb_bymva, tmp
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mov \tmp, #0
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mrc p15, 0, \tmp, c7, c5, 7 /* BPIMVA */
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.endm
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/************************************************************************************
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* Name: cp15_invalidate_dcacheline_bymva
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*
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* Description:
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* Invalidate data cache line by VA to PoC
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*
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* Input Parameters:
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* va - Register with VA format
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_invalidate_dcacheline_bymva, va
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mrc p15, 0, \va, c7, c6, 1 /* DCIMVAC */
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.endm
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/************************************************************************************
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* Name: cp15_invalidate_dcacheline_bysetway
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*
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* Description:
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* Invalidate data cache line by set/way
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*
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* Input Parameters:
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* setway - Register with Set/Way format
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_invalidate_dcacheline_bysetway, setway
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mrc p15, 0, \setway, c7, c6, 2 /* DCISW */
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.endm
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/************************************************************************************
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* Name: cp15_clean_dcache_bymva
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*
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* Description:
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* Clean data cache line by MVA
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*
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* Input Parameters:
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* va - Register with VA format
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_clean_dcache_bymva, va
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mrc p15, 0, \va, c7, c10, 1 /* DCCMVAC */
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.endm
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/************************************************************************************
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* Name: cp15_clean_dcache_bysetway
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*
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* Description:
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* Clean data cache line by Set/way
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*
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* Input Parameters:
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* setway - Register with Set/Way format
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_clean_dcache_bysetway, setway
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mrc p15, 0, \setway, c7, c10, 2 /* DCCSW */
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.endm
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/************************************************************************************
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* Name: cp15_clean_ucache_bymva
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*
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* Description:
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* Clean unified cache line by MVA
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*
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* Input Parameters:
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* setway - Register with VA format
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_clean_ucache_bymva, setway
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mrc p15, 0, \setway, c7, c11, 1 /* DCCMVAU */
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.endm
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/************************************************************************************
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* Name: cp15_cleaninvalidate_dcacheline_bymva
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*
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* Description:
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* Clean and invalidate data cache line by VA to PoC
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*
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* Input Parameters:
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* va - Register with VA format
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_cleaninvalidate_dcacheline_bymva, va
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mrc p15, 0, \va, c7, c14, 1 /* DCCIMVAC */
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.endm
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/************************************************************************************
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* Name: cp15_cleaninvalidate_dcacheline
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*
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* Description:
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* Clean and Incalidate data cache line by Set/Way
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*
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* Input Parameters:
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* setway - Register with Set/Way format
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.macro cp15_cleaninvalidate_dcacheline, setway
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mrc p15, 0, \setway, c7, c14, 2 /* DCCISW */
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.endm
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#endif /* __ASSEMBLY__ */
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Name: cp15_disable_dcache
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*
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* Description:
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* Disable L1 Caches
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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static inline void cp15_disable_dcache(void)
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{
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__asm__ __volatile__
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(
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"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
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"\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */
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"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
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:
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:
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: "r0", "memory"
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);
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}
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/************************************************************************************
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* Name: cp15_disable_caches
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*
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* Description:
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* Disable L1 Caches
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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static inline void cp15_disable_caches(void)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
|
|
"\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */
|
|
"\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */
|
|
"\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
|
|
:
|
|
:
|
|
: "r0", "memory"
|
|
);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: cp15_invalidate_icache_inner_sharable
|
|
*
|
|
* Description:
|
|
* Invalidate I cache predictor array inner sharable
|
|
*
|
|
* Input Parameters:
|
|
* None
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
************************************************************************************/
|
|
|
|
static inline void cp15_invalidate_icache_inner_sharable(void)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmov r0, #0\n"
|
|
"\tmcr p15, 0, r0, c7, c1, 0\n" /* ICIALLUIS */
|
|
:
|
|
:
|
|
: "r0", "memory"
|
|
);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: cp15_invalidate_btb_inner_sharable
|
|
*
|
|
* Description:
|
|
* Invalidate entire branch predictor array inner sharable
|
|
*
|
|
* Input Parameters:
|
|
* None
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
************************************************************************************/
|
|
|
|
static inline void cp15_invalidate_btb_inner_sharable(void)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmov r0, #0\n"
|
|
"\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */
|
|
:
|
|
:
|
|
: "r0", "memory"
|
|
);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: cp15_invalidate_icache
|
|
*
|
|
* Description:
|
|
* Invalidate all instruction caches to PoU, also flushes branch target cache
|
|
*
|
|
* Input Parameters:
|
|
* None
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
************************************************************************************/
|
|
|
|
static inline void cp15_invalidate_icache(void)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmov r0, #0\n"
|
|
"\tmcr p15, 0, r0, c7, c5, 0\n" /* ICIALLU */
|
|
:
|
|
:
|
|
: "r0", "memory"
|
|
);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: cp15_invalidate_icache_bymva
|
|
*
|
|
* Description:
|
|
* Invalidate instruction caches by VA to PoU
|
|
*
|
|
* Input Parameters:
|
|
* va - 32-bit value with VA format
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
************************************************************************************/
|
|
|
|
static inline void cp15_invalidate_icache_bymva(unsigned int va)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmcr p15, 0, %0, c7, c5, 1\n" /* ICIMVAU */
|
|
:
|
|
: "r" (va)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: cp15_flush_btb
|
|
*
|
|
* Description:
|
|
* Invalidate entire branch predictor array
|
|
*
|
|
* Input Parameters:
|
|
* None
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
************************************************************************************/
|
|
|
|
static inline void cp15_flush_btb(void)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmov r0, #0\n"
|
|
"\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */
|
|
:
|
|
:
|
|
: "r0", "memory"
|
|
);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: cp15_flush_btb_bymva
|
|
*
|
|
* Description:
|
|
* Invalidate branch predictor array entry by MVA
|
|
*
|
|
* Input Parameters:
|
|
* None
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
************************************************************************************/
|
|
|
|
static inline void cp15_flush_btb_bymva(void)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmov r0, #0\n"
|
|
"\tmcr p15, 0, r0, c7, c5, 7\n" /* BPIMVA */
|
|
:
|
|
:
|
|
: "r0", "memory"
|
|
);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: cp15_invalidate_dcacheline_bymva
|
|
*
|
|
* Description:
|
|
* Invalidate data cache line by VA to PoC
|
|
*
|
|
* Input Parameters:
|
|
* va - 32-bit value with VA format
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
************************************************************************************/
|
|
|
|
/* Invalidate data cache line by VA to PoC */
|
|
|
|
static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmcr p15, 0, %0, c7, c6, 1\n" /* DCIMVAC */
|
|
:
|
|
: "r" (va)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: cp15_invalidate_dcacheline_bysetway
|
|
*
|
|
* Description:
|
|
* Invalidate data cache line by set/way
|
|
*
|
|
* Input Parameters:
|
|
* setway - 32-bit value with Set/Way format
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
************************************************************************************/
|
|
|
|
/* Invalidate data cache line by set/way */
|
|
|
|
static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmcr p15, 0, %0, c7, c6, 2\n" /* DCISW */
|
|
:
|
|
: "r" (setway)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: cp15_clean_dcache_bymva
|
|
*
|
|
* Description:
|
|
* Clean data cache line by MVA
|
|
*
|
|
* Input Parameters:
|
|
* va - 32-bit value with VA format
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
************************************************************************************/
|
|
|
|
/* Clean data cache line by MVA */
|
|
|
|
static inline void cp15_clean_dcache_bymva(unsigned int va)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmcr p15, 0, %0, c7, c10, 1\n" /* DCCMVAC */
|
|
:
|
|
: "r" (va)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: cp15_clean_dcache_bysetway
|
|
*
|
|
* Description:
|
|
* Clean data cache line by Set/way
|
|
*
|
|
* Input Parameters:
|
|
* setway - 32-bit value with Set/Way format
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
************************************************************************************/
|
|
|
|
static inline void cp15_clean_dcache_bysetway(unsigned int setway)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmcr p15, 0, %0, c7, c10, 2\n" /* DCCSW */
|
|
:
|
|
: "r" (setway)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: cp15_clean_ucache_bymva
|
|
*
|
|
* Description:
|
|
* Clean unified cache line by MVA
|
|
*
|
|
* Input Parameters:
|
|
* setway - 32-bit value with VA format
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
************************************************************************************/
|
|
|
|
static inline void cp15_clean_ucache_bymva(unsigned int setway)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmcr p15, 0, %0, c7, c11, 1\n" /* DCCMVAU */
|
|
:
|
|
: "r" (setway)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: cp15_cleaninvalidate_dcacheline_bymva
|
|
*
|
|
* Description:
|
|
* Clean and invalidate data cache line by VA to PoC
|
|
*
|
|
* Input Parameters:
|
|
* va - 32-bit value with VA format
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
************************************************************************************/
|
|
|
|
static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmcr p15, 0, r0, c7, c14, 1\n" /* DCCIMVAC */
|
|
:
|
|
: "r" (va)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: cp15_cleaninvalidate_dcacheline
|
|
*
|
|
* Description:
|
|
* Clean and Incalidate data cache line by Set/Way
|
|
*
|
|
* Input Parameters:
|
|
* setway - 32-bit value with Set/Way format
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
************************************************************************************/
|
|
|
|
static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway)
|
|
{
|
|
__asm__ __volatile__
|
|
(
|
|
"\tmcr p15, 0, %0, c7, c14, 2\n" /* DCCISW */
|
|
:
|
|
: "r" (setway)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
/****************************************************************************
|
|
* Public Data
|
|
****************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
|
|
#ifdef __cplusplus
|
|
#define EXTERN extern "C"
|
|
extern "C"
|
|
{
|
|
#else
|
|
#define EXTERN extern
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Public Function Prototypes
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: cp15_coherent_dcache
|
|
*
|
|
* Description:
|
|
* Ensure that the I and D caches are coherent within specified region
|
|
* by cleaning the D cache (i.e., flushing the D cache contents to memory
|
|
* and invalidating the I cache). This is typically used when code has been
|
|
* written to a memory region, and will be executed.
|
|
*
|
|
* Input Parameters:
|
|
* start - virtual start address of region
|
|
* end - virtual end address of region + 1
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
****************************************************************************/
|
|
|
|
void cp15_coherent_dcache(uintptr_t start, uintptr_t end);
|
|
|
|
/****************************************************************************
|
|
* Name: cp15_invalidate_dcache
|
|
*
|
|
* Description:
|
|
* Invalidate the data cache within the specified region; we will be
|
|
* performing a DMA operation in this region and we want to purge old data
|
|
* in the cache.
|
|
*
|
|
* Input Parameters:
|
|
* start - virtual start address of region
|
|
* end - virtual end address of region + 1
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
****************************************************************************/
|
|
|
|
void cp15_invalidate_dcache(uintptr_t start, uintptr_t end);
|
|
|
|
/****************************************************************************
|
|
* Name: cp15_invalidate_dcache_all
|
|
*
|
|
* Description:
|
|
* Invalidate the entire contents of D cache.
|
|
*
|
|
* Input Parameters:
|
|
* None
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
****************************************************************************/
|
|
|
|
void cp15_invalidate_dcache_all(void);
|
|
|
|
/****************************************************************************
|
|
* Name: cp15_clean_dcache
|
|
*
|
|
* Description:
|
|
* Clean the data cache within the specified region by flushing the
|
|
* contents of the data cache to memory.
|
|
*
|
|
* Input Parameters:
|
|
* start - virtual start address of region
|
|
* end - virtual end address of region + 1
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
****************************************************************************/
|
|
|
|
void cp15_clean_dcache(uintptr_t start, uintptr_t end);
|
|
|
|
/****************************************************************************
|
|
* Name: cp15_flush_dcache
|
|
*
|
|
* Description:
|
|
* Flush the data cache within the specified region by cleaning and
|
|
* invalidating the D cache.
|
|
*
|
|
* Input Parameters:
|
|
* start - virtual start address of region
|
|
* end - virtual end address of region + 1
|
|
*
|
|
* Returned Value:
|
|
* None
|
|
*
|
|
****************************************************************************/
|
|
|
|
void cp15_flush_dcache(uintptr_t start, uintptr_t end);
|
|
|
|
#undef EXTERN
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#endif /* __ARCH_ARM_SRC_ARMV7_R_CP15_CACHEOPS_H */
|