2aa85fd17e
Summary The naming standard at https://cwiki.apache.org/confluence/display/NUTTX/Naming+FAQ requires that all MCU-private functions begin with the name of the architecture, not up_. This PR addresses only these name changes for the ARM-private functions prototyped in arm_internal.h This change to the files only modifies the name of called functions. nxstyle fixes were made for all core architecture files. However, there are well over 5000 additional complaints from MCU drivers and board logic that are unrelated to to this change but were affected by the name change. It is not humanly possible to fix all of these. I ask that this change be treated like other cosmetic changes that we have done which do not require full nxstyle compliance. Impact There should be not impact of this change (other that one step toward more consistent naming). Testing stm32f4discovery:netnsh
708 lines
21 KiB
C
708 lines
21 KiB
C
/****************************************************************************
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* arch/arm/src/lpc43xx/lpc43_uart.c
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*
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* Copyright (C) 2012, 2017, 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <nuttx/irq.h>
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#include <arch/board/board.h>
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#include "arm_internal.h"
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#include "arm_arch.h"
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#include "chip.h"
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#include "lpc43_config.h"
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#include "lpc43_pinconfig.h"
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#include "lpc43_rgu.h"
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#include "lpc43_cgu.h"
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#include "lpc43_ccu.h"
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#include "lpc43_uart.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef HAVE_SERIAL_CONSOLE
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/* Select UART parameters for the selected console */
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# if defined(CONFIG_USART0_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC43_USART0_BASE
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# define CONSOLE_BASEFREQ BOARD_USART0_BASEFREQ
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# define CONSOLE_BAUD CONFIG_USART0_BAUD
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# define CONSOLE_BITS CONFIG_USART0_BITS
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# define CONSOLE_PARITY CONFIG_USART0_PARITY
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# define CONSOLE_2STOP CONFIG_USART0_2STOP
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# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC43_UART1_BASE
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# define CONSOLE_BASEFREQ BOARD_UART1_BASEFREQ
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# define CONSOLE_BAUD CONFIG_UART1_BAUD
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# define CONSOLE_BITS CONFIG_UART1_BITS
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# define CONSOLE_PARITY CONFIG_UART1_PARITY
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# define CONSOLE_2STOP CONFIG_UART1_2STOP
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# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC43_USART2_BASE
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# define CONSOLE_BASEFREQ BOARD_USART2_BASEFREQ
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# define CONSOLE_BAUD CONFIG_USART2_BAUD
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# define CONSOLE_BITS CONFIG_USART2_BITS
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# define CONSOLE_PARITY CONFIG_USART2_PARITY
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# define CONSOLE_2STOP CONFIG_USART2_2STOP
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# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
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# define CONSOLE_BASE LPC43_USART3_BASE
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# define CONSOLE_BASEFREQ BOARD_USART3_BASEFREQ
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# define CONSOLE_BAUD CONFIG_USART3_BAUD
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# define CONSOLE_BITS CONFIG_USART3_BITS
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# define CONSOLE_PARITY CONFIG_USART3_PARITY
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# define CONSOLE_2STOP CONFIG_USART3_2STOP
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# elif defined(HAVE_SERIAL_CONSOLE)
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# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
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# endif
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/* Get word length setting for the console */
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# if CONSOLE_BITS == 5
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# define CONSOLE_LCR_WLS UART_LCR_WLS_5BIT
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# elif CONSOLE_BITS == 6
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# define CONSOLE_LCR_WLS UART_LCR_WLS_6BIT
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# elif CONSOLE_BITS == 7
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# define CONSOLE_LCR_WLS UART_LCR_WLS_7BIT
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# elif CONSOLE_BITS == 8
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# define CONSOLE_LCR_WLS UART_LCR_WLS_8BIT
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# elif defined(HAVE_SERIAL_CONSOLE)
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# error "Invalid CONFIG_UARTn_BITS setting for console "
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# endif
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/* Get parity setting for the console */
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# if CONSOLE_PARITY == 0
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# define CONSOLE_LCR_PAR 0
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# elif CONSOLE_PARITY == 1
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# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
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# elif CONSOLE_PARITY == 2
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# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
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# elif CONSOLE_PARITY == 3
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# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
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# elif CONSOLE_PARITY == 4
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# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
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# elif defined(HAVE_SERIAL_CONSOLE)
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# error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE"
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# endif
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/* Get stop-bit setting for the console and USART0/2/3, UART1 */
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# if CONSOLE_2STOP != 0
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# define CONSOLE_LCR_STOP UART_LCR_STOP
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# else
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# define CONSOLE_LCR_STOP 0
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# endif
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/* LCR and FCR values for the console */
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# define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | \
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CONSOLE_LCR_STOP)
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# define CONSOLE_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
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UART_FCR_RXRST | UART_FCR_FIFOEN)
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: arm_lowputc
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*
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* Description:
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* Output one byte on the serial console
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*
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****************************************************************************/
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void arm_lowputc(char ch)
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{
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#ifdef HAVE_SERIAL_CONSOLE
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/* Wait for the transmitter to be available */
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while ((getreg32(CONSOLE_BASE + LPC43_UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
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/* Send the character */
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putreg32((uint32_t)ch, CONSOLE_BASE + LPC43_UART_THR_OFFSET);
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#endif
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}
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/****************************************************************************
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* Name: lpc43_lowsetup
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*
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* Description:
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* This performs basic initialization of the UART used for the serial
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* console. Its purpose is to get the console output available as soon
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* as possible.
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*
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* The USART0/2/3 and UART1 peripherals are configured using the following
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* registers:
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*
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* 1. Baud rate: In the LCR register, set bit DLAB = 1. This enables access
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* to registers DLL and DLM for setting the baud rate. Also, if needed,
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* set the fractional baud rate in the fractional divider
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* 2. UART FIFO: Use bit FIFO enable (bit 0) in FCR register to
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* enable FIFO.
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* 3. Pins: Select UART pins through the PINSEL registers and pin modes
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* through the PINMODE registers. UART receive pins should not have
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* pull-down resistors enabled.
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* 4. Interrupts: To enable UART interrupts set bit DLAB = 0 in the LCRF
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* register. This enables access to IER. Interrupts are enabled
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* in the NVIC using the appropriate Interrupt Set Enable register.
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* 5. DMA: UART transmit and receive functions can operate with the
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* GPDMA controller.
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*
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****************************************************************************/
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void lpc43_lowsetup(void)
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{
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#ifdef HAVE_UART
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/* Enable clocking and for all console UART and disable power for
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* other UARTs
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*/
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#if defined(CONFIG_USART0_SERIAL_CONSOLE)
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lpc43_usart0_setup();
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#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
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lpc43_uart1_setup();
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#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
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lpc43_usart2_setup();
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#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
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lpc43_usart3_setup();
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#endif
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/* Configure the console (only) */
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#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
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/* Clear fifos */
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putreg32(UART_FCR_RXRST | UART_FCR_TXRST,
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CONSOLE_BASE + LPC43_UART_FCR_OFFSET);
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/* Set trigger */
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putreg32(UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8,
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CONSOLE_BASE + LPC43_UART_FCR_OFFSET);
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/* Set up the LCR */
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putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE + LPC43_UART_LCR_OFFSET);
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/* Set the BAUD divisor */
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lpc43_setbaud(CONSOLE_BASE, CONSOLE_BASEFREQ, CONSOLE_BAUD);
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/* Configure the FIFOs */
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putreg32(UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST | UART_FCR_RXRST |
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UART_FCR_FIFOEN, CONSOLE_BASE + LPC43_UART_FCR_OFFSET);
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#endif
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#endif /* HAVE_UART */
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}
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/****************************************************************************
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* Name: lpc43_u[s]art0/1/2/3_reset
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*
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* Description:
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* Reset a UART. These functions are used by the serial driver when a
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* UART is closed.
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*
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****************************************************************************/
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#ifdef CONFIG_LPC43_USART0
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void lpc43_usart0_reset(void)
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{
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putreg32(RGU_CTRL1_USART0_RST, LPC43_RGU_CTRL1);
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}
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#endif
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#ifdef CONFIG_LPC43_UART1
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void lpc43_uart1_reset(void)
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{
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putreg32(RGU_CTRL1_UART1_RST, LPC43_RGU_CTRL1);
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}
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#endif
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#ifdef CONFIG_LPC43_USART2
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void lpc43_usart2_reset(void)
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{
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putreg32(RGU_CTRL1_USART2_RST, LPC43_RGU_CTRL1);
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}
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#endif
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#ifdef CONFIG_LPC43_USART3
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void lpc43_usart3_reset(void)
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{
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putreg32(RGU_CTRL1_USART3_RST, LPC43_RGU_CTRL1);
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}
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#endif
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/****************************************************************************
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* Name: lpc43_usart0_setup, lpc43_uart1_setup, lpc43_usart2_setup, and
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* lpc43_usart3_setup
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*
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* Description:
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* Configure the U[S]ART. This involves:
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*
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* 1. Connecting the input clock to the U[S]ART as specified in the
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* board.h file,
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* 2. Configuring the U[S]ART pins
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*
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* USART0/2/3 and UART1 clocking and power control:
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*
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* ----------------------------------- -------------- --------------
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* BASE CLOCK BRANCH CLOCK
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* ----------------------------------- -------------- --------------
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* USART0 clock to register interface BASE_M4_CLK CLK_M4_USART0
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* USART0 peripheral clock (PCLK) BASE_UART0_CLK CLK_APB0_UART0
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* UART1 clock to register interface BASE_M4_CLK CLK_M4_UART1
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* UART1 peripheral clock (PCLK) BASE_UART1_CLK CLK_APB0_UART1
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* USART2 clock to register interface BASE_M4_CLK CLK_M4_USART2
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* USART2 peripheral clock (PCLK) BASE_UART2_CLK CLK_APB2_UART2
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* USART3 clock to register interface BASE_M4_CLK CLK_M4_USART3
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* USART3 peripheral clock (PCLK) BASE_UART3_CLK CLK_APB2_UART3
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* ----------------------------------- -------------- --------------
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*
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****************************************************************************/
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#ifdef CONFIG_LPC43_USART0
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void lpc43_usart0_setup(void)
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{
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uint32_t regval;
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irqstate_t flags;
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/* Connect USART0 into the clock source specified in board.h */
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flags = enter_critical_section();
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regval = getreg32(LPC43_BASE_USART0_CLK);
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regval &= ~BASE_USART0_CLK_CLKSEL_MASK;
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regval |= (BOARD_USART0_CLKSRC | BASE_USART0_CLK_AUTOBLOCK);
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putreg32(regval, LPC43_BASE_USART0_CLK);
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/* Clock register */
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regval = getreg32(LPC43_CCU1_M4_USART0_CFG);
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regval |= CCU_CLK_CFG_RUN;
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putreg32(regval, LPC43_CCU1_M4_USART0_CFG);
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/* Clock peripheral */
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regval = getreg32(LPC43_CCU2_APB0_USART0_CFG);
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regval |= CCU_CLK_CFG_RUN;
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putreg32(regval, LPC43_CCU2_APB0_USART0_CFG);
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/* Configure I/O pins. NOTE that multiple pin configuration options must
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* be disambiguated by defining the pin configuration in the board.h
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* header file.
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*/
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lpc43_pin_config(PINCONF_U0_TXD);
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lpc43_pin_config(PINCONF_U0_RXD);
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/* If USART RS-485 mode is selected, then configure the DIR pin as well.
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* NOTE, again, that multiple pin configuration options must be
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* disambiguated by defining the pin configuration in the board.h header
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* file.
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*/
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#ifdef CONFIG_USART0_RS485MODE
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lpc43_pin_config(PINCONF_U0_DIR);
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/* Enable direction output pin */
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regval = getreg32(LPC43_USART0_RS485CTRL);
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regval |= UART_RS485CTRL_DCTRL;
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putreg32(regval, LPC43_USART0_RS485CTRL);
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#ifdef CONFIG_USART0_RS485DIROIN
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/* Invert direction control output pin polarity */
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regval = getreg32(LPC43_USART0_RS485CTRL);
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regval |= UART_RS485CTRL_OINV;
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putreg32(regval, LPC43_USART0_RS485CTRL);
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#else
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/* Do not invert direction countrol output pin polarity */
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regval = getreg32(LPC43_USART0_RS485CTRL);
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regval &= ~(UART_RS485CTRL_OINV);
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putreg32(regval, LPC43_USART0_RS485CTRL);
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#endif /* CONFIG_USART0_RS485DIROIN */
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#endif /* CONFIG_USART0_RS485MODE */
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leave_critical_section(flags);
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};
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#endif
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#ifdef CONFIG_LPC43_UART1
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void lpc43_uart1_setup(void)
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{
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uint32_t regval;
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irqstate_t flags;
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/* Connect UART1 into the clock source specified in board.h */
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flags = enter_critical_section();
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regval = getreg32(LPC43_BASE_UART1_CLK);
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regval &= ~BASE_UART1_CLK_CLKSEL_MASK;
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regval |= (BOARD_UART1_CLKSRC | BASE_UART1_CLK_AUTOBLOCK);
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putreg32(regval, LPC43_BASE_UART1_CLK);
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/* Clock register */
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regval = getreg32(LPC43_CCU1_M4_UART1_CFG);
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regval |= CCU_CLK_CFG_RUN;
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putreg32(regval, LPC43_CCU1_M4_UART1_CFG);
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/* Clock peripheral */
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regval = getreg32(LPC43_CCU2_APB0_UART1_CFG);
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regval |= CCU_CLK_CFG_RUN;
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putreg32(regval, LPC43_CCU2_APB0_UART1_CFG);
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/* Configure I/O pins. NOTE that multiple pin configuration options must
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* be disambiguated by defining the pin configuration in the board.h
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* header file.
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*/
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lpc43_pin_config(PINCONF_U1_TXD);
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lpc43_pin_config(PINCONF_U1_RXD);
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#ifdef CONFIG_UART1_FLOWCONTROL
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lpc43_pin_config(PINCONF_U1_CTS);
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lpc43_pin_config(PINCONF_U1_DCD);
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lpc43_pin_config(PINCONF_U1_DSR);
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lpc43_pin_config(PINCONF_U1_DTR);
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lpc43_pin_config(PINCONF_U1_RTS);
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#ifdef CONFIG_LPC43_UART1_RINGINDICATOR
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lpc43_pin_config(PINCONF_U1_RI);
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#endif
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#endif
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#ifdef CONFIG_UART1_RS485MODE
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lpc43_pin_config(PINCONF_U1_DIR);
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#endif
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leave_critical_section(flags);
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};
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#endif
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#ifdef CONFIG_LPC43_USART2
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void lpc43_usart2_setup(void)
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{
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uint32_t regval;
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irqstate_t flags;
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/* Connect USART2 the clock source specified in board.h */
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flags = enter_critical_section();
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regval = getreg32(LPC43_BASE_USART2_CLK);
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regval &= ~BASE_USART2_CLK_CLKSEL_MASK;
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regval |= (BOARD_USART2_CLKSRC | BASE_USART2_CLK_AUTOBLOCK);
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putreg32(regval, LPC43_BASE_USART2_CLK);
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/* Clock register */
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regval = getreg32(LPC43_CCU1_M4_USART2_CFG);
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regval |= CCU_CLK_CFG_RUN;
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putreg32(regval, LPC43_CCU1_M4_USART2_CFG);
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/* Clock peripheral */
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regval = getreg32(LPC43_CCU2_APB2_USART2_CFG);
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regval |= CCU_CLK_CFG_RUN;
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putreg32(regval, LPC43_CCU2_APB2_USART2_CFG);
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/* Configure I/O pins. NOTE that multiple pin configuration options must
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* be disambiguated by defining the pin configuration in the board.h
|
|
* header file.
|
|
*/
|
|
|
|
lpc43_pin_config(PINCONF_U2_TXD);
|
|
lpc43_pin_config(PINCONF_U2_RXD);
|
|
|
|
/* If USART RS-485 mode is selected, then configure the DIR pin as well.
|
|
* NOTE, again, that multiple pin configuration options must be
|
|
* disambiguated by defining the pin configuration in the board.h header
|
|
* file.
|
|
*/
|
|
|
|
#ifdef CONFIG_USART2_RS485MODE
|
|
lpc43_pin_config(PINCONF_U2_DIR);
|
|
|
|
/* Enable direction output pin */
|
|
|
|
regval = getreg32(LPC43_USART2_RS485CTRL);
|
|
regval |= UART_RS485CTRL_DCTRL;
|
|
putreg32(regval, LPC43_USART2_RS485CTRL);
|
|
|
|
#ifdef CONFIG_USART2_RS485DIROIN
|
|
|
|
/* Invert direction control output pin polarity */
|
|
|
|
regval = getreg32(LPC43_USART2_RS485CTRL);
|
|
regval |= UART_RS485CTRL_OINV;
|
|
putreg32(regval, LPC43_USART2_RS485CTRL);
|
|
|
|
#else
|
|
|
|
/* Do not invert direction countrol output pin polarity */
|
|
|
|
regval = getreg32(LPC43_USART2_RS485CTRL);
|
|
regval &= ~(UART_RS485CTRL_OINV);
|
|
putreg32(regval, LPC43_USART2_RS485CTRL);
|
|
|
|
#endif /* CONFIG_USART2_RS485DIROIN */
|
|
#endif /* CONFIG_USART2_RS485MODE */
|
|
|
|
leave_critical_section(flags);
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_LPC43_USART3
|
|
void lpc43_usart3_setup(void)
|
|
{
|
|
uint32_t regval;
|
|
irqstate_t flags;
|
|
|
|
/* Connect USART3 into the clock source specified in board.h */
|
|
|
|
flags = enter_critical_section();
|
|
|
|
regval = getreg32(LPC43_BASE_USART3_CLK);
|
|
regval &= ~BASE_USART3_CLK_CLKSEL_MASK;
|
|
regval |= (BOARD_USART3_CLKSRC | BASE_USART3_CLK_AUTOBLOCK);
|
|
putreg32(regval, LPC43_BASE_USART3_CLK);
|
|
|
|
/* Clock register */
|
|
|
|
regval = getreg32(LPC43_CCU1_M4_USART3_CFG);
|
|
regval |= CCU_CLK_CFG_RUN;
|
|
putreg32(regval, LPC43_CCU1_M4_USART3_CFG);
|
|
|
|
/* Clock peripheral */
|
|
|
|
regval = getreg32(LPC43_CCU2_APB2_USART3_CFG);
|
|
regval |= CCU_CLK_CFG_RUN;
|
|
putreg32(regval, LPC43_CCU2_APB2_USART3_CFG);
|
|
|
|
/* Configure I/O pins. NOTE that multiple pin configuration options must
|
|
* be disambiguated by defining the pin configuration in the board.h
|
|
* header file.
|
|
*/
|
|
|
|
lpc43_pin_config(PINCONF_U3_TXD);
|
|
lpc43_pin_config(PINCONF_U3_RXD);
|
|
|
|
/* If USART RS-485 mode is selected, then configure the DIR pin as well.
|
|
* NOTE, again, that multiple pin configuration options must be
|
|
* disambiguated by defining the pin configuration in the board.h header
|
|
* file.
|
|
*/
|
|
|
|
#ifdef CONFIG_USART3_RS485MODE
|
|
lpc43_pin_config(PINCONF_U3_DIR);
|
|
|
|
/* Enable direction output pin */
|
|
|
|
regval = getreg32(LPC43_USART3_RS485CTRL);
|
|
regval |= UART_RS485CTRL_DCTRL;
|
|
putreg32(regval, LPC43_USART3_RS485CTRL);
|
|
|
|
#ifdef CONFIG_USART3_RS485DIROIN
|
|
|
|
/* Invert direction control output pin polarity */
|
|
|
|
regval = getreg32(LPC43_USART3_RS485CTRL);
|
|
regval |= UART_RS485CTRL_OINV;
|
|
putreg32(regval, LPC43_USART3_RS485CTRL);
|
|
|
|
#else
|
|
|
|
/* Do not invert direction countrol output pin polarity */
|
|
|
|
regval = getreg32(LPC43_USART3_RS485CTRL);
|
|
regval &= ~(UART_RS485CTRL_OINV);
|
|
putreg32(regval, LPC43_USART3_RS485CTRL);
|
|
|
|
#endif /* CONFIG_USART3_RS485DIROIN */
|
|
#endif /* CONFIG_USART3_RS485MODE */
|
|
|
|
leave_critical_section(flags);
|
|
};
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: lpc43_setbaud
|
|
*
|
|
* Description:
|
|
* Configure the U[S]ART divisors to accomplish the desired BAUD given the
|
|
* U[S]ART base frequency.
|
|
*
|
|
* This computationally intensive algorithm is based on the same logic
|
|
* used in the NXP sample code.
|
|
*
|
|
****************************************************************************/
|
|
|
|
void lpc43_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
|
|
{
|
|
uint32_t lcr; /* Line control register value */
|
|
uint32_t dl; /* Best DLM/DLL full value */
|
|
uint32_t mul; /* Best FDR MULVALL value */
|
|
uint32_t divadd; /* Best FDR DIVADDVAL value */
|
|
uint32_t best; /* Error value associated with best {dl, mul, divadd} */
|
|
uint32_t cdl; /* Candidate DLM/DLL full value */
|
|
uint32_t cmul; /* Candidate FDR MULVALL value */
|
|
uint32_t cdivadd; /* Candidate FDR DIVADDVAL value */
|
|
uint32_t errval; /* Error value associated with the candidate */
|
|
|
|
/* The U[S]ART baud is given by:
|
|
*
|
|
* Fbaud = Fbase * mul / (mul + divadd) / (16 * dl)
|
|
* dl = Fbase * mul / (mul + divadd) / Fbaud / 16
|
|
* = Fbase * mul / ((mul + divadd) * Fbaud * 16)
|
|
* = ((Fbase * mul) >> 4) / ((mul + divadd) * Fbaud)
|
|
*
|
|
* Where the value of MULVAL and DIVADDVAL comply with:
|
|
*
|
|
* 0 < mul < 16
|
|
* 0 <= divadd < mul
|
|
*/
|
|
|
|
best = UINT32_MAX;
|
|
divadd = 0;
|
|
mul = 0;
|
|
dl = 0;
|
|
|
|
/* Try each multiplier value in the valid range */
|
|
|
|
for (cmul = 1 ; cmul < 16; cmul++)
|
|
{
|
|
/* Try each divider value in the valid range */
|
|
|
|
for (cdivadd = 0 ; cdivadd < cmul ; cdivadd++)
|
|
{
|
|
/* Candidate:
|
|
* dl = ((Fbase * mul) >> 4) / ((mul + cdivadd) * Fbaud)
|
|
* (dl << 32) = (Fbase << 28) * cmul / ((mul + cdivadd) * Fbaud)
|
|
*/
|
|
|
|
uint64_t dl64 = ((uint64_t)basefreq << 28) * cmul /
|
|
((cmul + cdivadd) * baud);
|
|
|
|
/* The lower 32-bits of this value is the error */
|
|
|
|
errval = (uint32_t)(dl64 & 0x00000000ffffffffull);
|
|
|
|
/* The upper 32-bits is the candidate DL value */
|
|
|
|
cdl = (uint32_t)(dl64 >> 32);
|
|
|
|
/* Round up */
|
|
|
|
if (errval > (1 << 31))
|
|
{
|
|
errval = -errval;
|
|
cdl++;
|
|
}
|
|
|
|
/* Check if the resulting candidate DL value is within range */
|
|
|
|
if (cdl < 1 || cdl > 65536)
|
|
{
|
|
/* No... try a different divadd value */
|
|
|
|
continue;
|
|
}
|
|
|
|
/* Is this the best combination that we have seen so far? */
|
|
|
|
if (errval < best)
|
|
{
|
|
/* Yes.. then the candidate is out best guess so far */
|
|
|
|
best = errval;
|
|
dl = cdl;
|
|
divadd = cdivadd;
|
|
mul = cmul;
|
|
|
|
/* If the new best guess is exact (within our precision), then
|
|
* we are finished.
|
|
*/
|
|
|
|
if (best == 0)
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
DEBUGASSERT(dl > 0);
|
|
|
|
/* Enter DLAB=1 */
|
|
|
|
lcr = getreg32(uartbase + LPC43_UART_LCR_OFFSET);
|
|
putreg32(lcr | UART_LCR_DLAB, uartbase + LPC43_UART_LCR_OFFSET);
|
|
|
|
/* Save the divider values */
|
|
|
|
putreg32(dl >> 8, uartbase + LPC43_UART_DLM_OFFSET);
|
|
putreg32(dl & 0xff, uartbase + LPC43_UART_DLL_OFFSET);
|
|
|
|
/* Clear DLAB */
|
|
|
|
putreg32(lcr & ~UART_LCR_DLAB, uartbase + LPC43_UART_LCR_OFFSET);
|
|
|
|
/* Then save the fractional divider values */
|
|
|
|
putreg32((mul << UART_FDR_MULVAL_SHIFT) | (divadd << UART_FDR_DIVADDVAL_SHIFT),
|
|
uartbase + LPC43_UART_FDR_OFFSET);
|
|
}
|