71 lines
2.3 KiB
ReStructuredText
71 lines
2.3 KiB
ReStructuredText
======================================
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Enjoy Digital LiteX FPGA's
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======================================
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The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and create full FPGA based systems.
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Information specific to Litex and supported boards can be found on the project's homepage: https://github.com/enjoy-digital/litex
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Nuttx has basic support for two softcores
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- vexriscv: FPGA friendly RISC-V ISA CPU implementation
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- vexriscv_smp: A more fully featured, Linux compatible core.
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Currently, the only configured development board in the Arty A7 https://digilent.com/reference/programmable-logic/arty-a7/start. However, many Litex supported boards
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should work with either core, requiring minimal adjustment to the configuration.
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Toolchain
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==============
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Litex projects can be built with a generic RISC-V GCC toolchain. There are currently two options.
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Prebuilt toolchain
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------------------
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A prebuilt RISC-V toolchain from SiFive can be used to build Litex projects::
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# Download the prebuilt toolchain
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$ curl https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz \
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> riscv64-unknown-elf-gcc.tar.gz
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# Unpack the archive
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$ tar -xf riscv64-unknown-elf-gcc.tar.gz
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# Add to path
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$ export PATH="$HOME/path/to/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin:$PATH
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Custom built toolchain
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----------------------
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The toolchain needs to be compiled locally in order to use a more modern version. At the time of writing,
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the source can be obtained from https://github.com/riscv-collab/riscv-gnu-toolchain and built with the following configuration::
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$ CFLAGS="-g0 -Os"
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$ CXXFLAGS="-g0 -Os"
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$ LDFLAGS="-s"
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$ ./configure \
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CFLAGS_FOR_TARGET='-O2 -mcmodel=medany' \
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CXXFLAGS_FOR_TARGET='-O2 -mcmodel=medany' \
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--prefix=path/to/install/to \
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--with-system-zlib \
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--with-arch=rv32ima \
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--with-abi=ilp32
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$ make
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.. important:: The vexriscv_smp core requires `with-arch=rv32imac`.
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Check the linked github repository for other options, including building with multilib enabled.
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Core specific information
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=========================
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.. toctree::
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:glob:
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:maxdepth: 1
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cores/*/*
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