67 lines
2.5 KiB
C
67 lines
2.5 KiB
C
/****************************************************************************
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* arch/arm/src/lpc17xx_40xx/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC17XX_40XX_CHIP_H
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#define __ARCH_ARM_SRC_LPC17XX_40XX_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "nvic.h"
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/* Include the chip capabilities file */
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#include <arch/lpc17xx_40xx/chip.h>
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/* Include the chip interrupt definition file */
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#include <arch/lpc17xx_40xx/irq.h>
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/* Include the memory map file. Other chip hardware files should then
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* include this file for the proper setup.
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*/
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#include "hardware/lpc17_40_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Provide the required number of peripheral interrupt vector definitions as
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* well. The definition LPC17_40_IRQ_NEXTINT simply comes from the
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* chip-specific IRQ header file included by arch/lpc17xx_40xx/irq.h.
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*/
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#define ARMV7M_PERIPHERAL_INTERRUPTS LPC17_40_IRQ_NEXTINT
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/* Vector Table Offset Register (VECTAB). Redefine the mask defined in
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* arch/arm/src/armv7-m/nvic.h; The LPC178x/7x User manual definitions
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* do not match the ARMv7M field definitions. Any bits set above bit
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* 29 would be an error and apparently the register wants 8- not 6-bit
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* alignment.
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*/
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#undef NVIC_VECTAB_TBLOFF_MASK
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#define NVIC_VECTAB_TBLOFF_MASK (0x3fffff00)
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#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_CHIP_H */
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