Gregory Nutt 7113cef6b7 Squashed commit of the following: ...

arch/arm/src/tiva:  Add CC13xx logic to enable power domains needed by peripherals and to enable clocking to peripherals.

    arch/arm/src/tiva:  Rename some header files so that they are unique in order to avoid including the wrong file.  Fix various compile issues found during some initial trial builds.

    arch/arm/src/tiva:  Add CC13xx clock enable and power enable macros that are backward compatible with lm/tm4c macros.

2018-12-09 07:03:10 -06:00

..

a1x

Standardize the width of all comment boxes in header files

2015-10-02 17:42:29 -06:00

arm

arch/arm: (1) Add semihost support for syslog, (2) Add semihost support for HostFS

2018-08-23 08:00:07 -06:00

armv6-m

arch/arm: (1) Add semihost support for syslog, (2) Add semihost support for HostFS

2018-08-23 08:00:07 -06:00

armv7-a

arch/arm: (1) Add semihost support for syslog, (2) Add semihost support for HostFS

2018-08-23 08:00:07 -06:00

armv7-m

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

armv7-r

arch/arm: (1) Add semihost support for syslog, (2) Add semihost support for HostFS

2018-08-23 08:00:07 -06:00

bcm2708

arch/: Clean up some naming and spacing.

2018-06-20 15:38:06 -06:00

c5471

Standardize the width of all comment boxes in header files

2015-10-02 17:42:29 -06:00

dm320

Standardize the width of all comment boxes in header files

2015-10-02 17:42:29 -06:00

efm32

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

imx1

i.MX6: Add IRQ header file

2016-02-28 14:07:53 -06:00

imx6

Fix lots of typos in C comments and Kconfig help text

2018-07-08 18:24:45 -06:00

imxrt

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

kinetis

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

kl

arch/: Clean up some naming and spacing.

2018-06-20 15:38:06 -06:00

lc823450

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

lpc11xx

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

lpc17xx

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

lpc31xx

Standardize the width of all comment boxes in header files

2015-10-02 17:42:29 -06:00

lpc43xx

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

lpc54xx

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

lpc214x

Fix names of pre-processor variables used in header file idempotence

2016-08-06 18:48:45 -06:00

lpc2378

Fix names of pre-processor variables used in header file idempotence

2016-08-06 18:48:45 -06:00

max326xx

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

moxart

Standardize the width of all comment boxes in header files

2015-10-02 17:42:29 -06:00

nrf52

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

nuc1xx

Cosmetic changes to spacing and comments.

2017-04-20 14:08:08 -06:00

sam34

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

sama5

Standardize the width of all comment boxes in header files

2015-10-02 17:42:29 -06:00

samd2l2

Rename all usage of samdl/SAMDL to samd2l2/SAMD2L2 to make room in the name space for the forthcoming samd5e5/SAMD5E5

2018-07-22 15:54:12 -06:00

samd5e5

configs/metro-m4: Fix RxD interrupt pin selection. The number SERCOM interrupts do not refer to PAD numbers, but to bit positions in the INFLAG register (very tiny footnote in the data sheet). With with final fix, the basic NSH configuration appears fully functional.

2018-09-01 15:29:22 -06:00

samv7

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

stm32

Merged in raiden00/nuttx_pe (pull request #776)

2018-12-06 17:52:11 +00:00

stm32f0

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

stm32f7

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

stm32h7

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

stm32l4

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

str71x

Clean up and review of header files for conformance to standards

2015-06-12 19:26:01 -06:00

tiva

Squashed commit of the following:

2018-12-09 07:03:10 -06:00

tms570

arch/arm/include/tms570, arm/src/armv7-r, and arm/src/tms570: Adds support for the TMS570LS3137ZWT and corrects seversl ARMv7-R and TMS570 issues

2018-04-18 08:58:36 -06:00

xmc4

In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts.

2018-12-03 17:41:59 -06:00

.gitignore

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arch.h

Standardize the width of all comment boxes in header files

2015-10-02 17:42:29 -06:00

elf.h

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inttypes.h

Add architecture-specific inttypes.h

2016-10-27 16:01:38 -04:00

irq.h

Squashed commit of the following:

2017-10-09 13:11:17 -06:00

limits.h

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serial.h

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spinlock.h

armv7-a, armv7-r, armv7-m: Add atomic read-add-write and read-subtract-write functions.

2018-02-04 12:22:03 -06:00

stdarg.h

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syscall.h

Standardize the width of all comment boxes in header files

2015-10-02 17:42:29 -06:00

tls.h

TLS: Forgot to add a file before last commit

2016-03-11 12:30:04 -06:00

types.h

Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore()

2016-02-14 16:11:25 -06:00

watchdog.h

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