221 lines
8.4 KiB
C
221 lines
8.4 KiB
C
/****************************************************************************
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* arch/arm/src/imx6/imx_memorymap.c
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "mmu.h"
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#include "hardware/imx_memorymap.h"
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#include "imx_memorymap.h"
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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/* This table describes how to map a set of 1Mb pages to space the physical
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* address space of the i.MX6.
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*/
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const struct section_mapping_s g_section_mapping[] =
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{
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/* i.MX6 Address Sections Memories */
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/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
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* beginning of the .text region must appear at address at the address
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* specified in the VBAR. There are two ways to accomplish this:
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*
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* 1. By explicitly mapping the beginning of .text region with a page
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* table entry so that the virtual address zero maps to the beginning
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* of the .text region. VBAR == 0x0000:0000.
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*
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* 2. Set the Cortex-A5 VBAR register so that the vector table address
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* is moved to a location other than 0x0000:0000.
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*
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* This is the method used by this logic.
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*
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* The system always boots from the ROM memory at address 0x0. After
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* reset, and until the Remap command is performed, the OCRAM is accessible
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* at address 0x0090 0000.
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*
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* If we are executing from external SDRAM, then a secondary bootloader must
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* have loaded us into SDRAM. In this case, simply set the VBAR register
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* to the address of the vector table (not necessary at the beginning
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* or SDRAM).
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*/
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{ IMX_ROMCP_PSECTION, IMX_ROMCP_VSECTION, /* Boot ROM (ROMCP) */
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IMX_ROMCP_MMUFLAGS, IMX_ROMCP_NSECTIONS
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},
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{ IMX_DMA_PSECTION, IMX_DMA_VSECTION, /* "DMA" sectinon peripherals */
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IMX_DMA_MMUFLAGS, IMX_DMA_NSECTIONS
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},
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{ IMX_GPV2_PSECTION, IMX_GPV2_VSECTION, /* GPV_2 PL301 (per1) configuration port */
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IMX_GPV2_MMUFLAGS, IMX_GPV2_NSECTIONS
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},
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{ IMX_GPV3_PSECTION, IMX_GPV3_VSECTION, /* GPV_3 PL301 (per2) configuration port */
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IMX_GPV3_MMUFLAGS, IMX_GPV3_NSECTIONS
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},
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{ IMX_GPV4_PSECTION, IMX_GPV4_VSECTION, /* GPV_4 PL301 (fast3) configuration port */
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IMX_GPV4_MMUFLAGS, IMX_GPV4_NSECTIONS
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},
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{ IMX_OCRAM_PSECTION, IMX_OCRAM_VSECTION, /* OCRAM */
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IMX_OCRAM_MMUFLAGS, IMX_OCRAM_NSECTIONS
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},
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{ IMX_ARMMP_PSECTION, IMX_ARMMP_VSECTION, /* ARM MP */
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IMX_ARMMP_MMUFLAGS, IMX_ARMMP_NSECTIONS
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},
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{ IMX_GPV0PL301_PSECTION, IMX_GPV0PL301_VSECTION, /* GPV0 PL301 (fast2) configuration port */
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IMX_GPV0PL301_MMUFLAGS, IMX_GPV0PL301_NSECTIONS
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},
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{ IMX_GPV1PL301_PSECTION, IMX_GPV1PL301_VSECTION, /* GPV1 PL301 (fast1) configuration port */
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IMX_GPV1PL301_MMUFLAGS, IMX_GPV1PL301_NSECTIONS
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},
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{ IMX_PCIE_PSECTION, IMX_PCIE_VSECTION, /* PCIe */
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IMX_PCIE_MMUFLAGS, IMX_PCIE_NSECTIONS
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},
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{ IMX_AIPS1_PSECTION, IMX_AIPS1_VSECTION, /* Peripheral IPs via AIPS-1 */
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IMX_AIPS1_MMUFLAGS, IMX_AIPS1_NSECTIONS
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},
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{ IMX_AIPS2_PSECTION, IMX_AIPS2_VSECTION, /* Peripheral IPs via AIPS-2 */
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IMX_AIPS2_MMUFLAGS, IMX_AIPS2_NSECTIONS
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},
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{ IMX_SATA_PSECTION, IMX_SATA_VSECTION, /* SATA */
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IMX_SATA_MMUFLAGS, IMX_SATA_NSECTIONS
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},
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{ IMX_IPU1_PSECTION, IMX_IPU1_VSECTION, /* IPU-1 */
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IMX_IPU1_MMUFLAGS, IMX_IPU1_NSECTIONS
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},
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{ IMX_IPU2_PSECTION, IMX_IPU2_VSECTION, /* IPU-2 */
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IMX_IPU2_MMUFLAGS, IMX_IPU2_NSECTIONS
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},
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#ifdef CONFIG_IMX6_EIM
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{ IMX_EIM_PSECTION, IMX_EIM_VSECTION, /* EIM - (NOR/SRAM) */
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IMX_EIM_MMUFLAGS, IMX_EIM_NSECTIONS
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},
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#endif
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/* i.MX6 External SDRAM Memory. The SDRAM is not usable until it has been
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* initialized. If we are running out of SDRAM now, we can assume that some
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* second level boot loader has properly configured SRAM for us. In that
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* case, we set the MMU flags for the final, fully cache-able state.
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*
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* Also, in this case, the mapping for the SDRAM was done in arm_head.S and
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* need not be repeated here.
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*
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* If we are running from OCRAM or NOR flash, then we will need to configure
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* the SDRAM ourselves. In this case, we set the MMU flags to the strongly
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* ordered, non-cacheable state. We need this direct access to SDRAM in
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* order to configure it. Once SDRAM has been initialized, it will be re-
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* configured in its final state.
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*/
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#ifdef NEED_SDRAM_MAPPING
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{ IMX_MMDCDDR_PSECTION, IMX_MMDCDDR_VSECTION, /* MMDC-DDR Controller */
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MMU_STRONGLY_ORDERED, IMX_MMDCDDR_NSECTIONS
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},
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#else
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{ IMX_MMDCDDR_PSECTION, IMX_MMDCDDR_VSECTION, /* MMDC-DDR Controller */
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IMX_MMDCDDR_MMUFLAGS, IMX_MMDCDDR_NSECTIONS
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},
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#endif
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/* LCDC Framebuffer. This entry reprograms a part of one of the above
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* regions, making it non-cacheable and non-buffereable.
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*
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* If SDRAM will be reconfigured, then we will defer setup of the framebuffer
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* until after the SDRAM remapping (since the framebuffer problem resides) in
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* SDRAM.
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*/
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#if defined(CONFIG_IMX6_LCDC) && !defined(NEED_SDRAM_REMAPPING)
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{ CONFIG_IMX6_LCDC_FB_PBASE, CONFIG_IMX6_LCDC_FB_VBASE,
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MMU_IOFLAGS, IMX6_LCDC_FBNSECTIONS
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},
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#endif
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};
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/* The number of entries in the mapping table */
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#define NMAPPINGS \
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(sizeof(g_section_mapping) / sizeof(struct section_mapping_s))
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const size_t g_num_mappings = NMAPPINGS;
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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/* i.MX6 External SDRAM Memory. Final configuration. The SDRAM was
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* configured in a temporary state to support low-level ininitialization.
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* After the SDRAM has been fully initialized, this structure is used to
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* set the SDRM in its final, fully cache-able state.
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*/
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#ifdef NEED_SDRAM_REMAPPING
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const struct section_mapping_s g_operational_mapping[] =
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{
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/* This entry reprograms the SDRAM entry, making it cacheable and
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* bufferable.
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*/
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{ IMX_MMDCDDR_PSECTION, IMX_MMDCDDR_VSECTION, /* MMDC-DDR Controller */
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IMX_MMDCDDR_MMUFLAGS, IMX_MMDCDDR_NSECTIONS
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},
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/* LCDC Framebuffer. This entry reprograms a part of one of the above
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* regions, making it non-cacheable and non-buffereable.
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*/
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#ifdef CONFIG_IMX6_LCDC
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{CONFIG_IMX6_LCDC_FB_PBASE, CONFIG_IMX6_LCDC_FB_VBASE,
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MMU_IOFLAGS, IMX6_LCDC_FBNSECTIONS
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},
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#endif
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};
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/* The number of entries in the operational mapping table */
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#define NREMAPPINGS \
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(sizeof(g_operational_mapping) / sizeof(struct section_mapping_s))
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const size_t g_num_opmappings = NREMAPPINGS;
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#endif /* NEED_SDRAM_REMAPPING */
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