Gregory Nutt c300f27130 arch/arm/include/armv7-m/nvicpri.h: In the 'normal' case, the priority of the SVCALL interrupt was the same as the priority of the high priority interrupt. This means that SVCALL interrupt processing can defer the high priority interrupt and result in the jitter in that interrupt response. Fix is to raise the priority of the high priority interrupt above the priority of the SVCALL interrupt. Suggested by Nathan Hartman.		2019-08-09 07:07:16 -06:00
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irq_cmnvector.h
irq_lazyfpu.h
irq.h	Squashed commit of the following:	2019-04-29 14:52:05 -06:00
nvicpri.h	arch/arm/include/armv7-m/nvicpri.h: In the 'normal' case, the priority of the SVCALL interrupt was the same as the priority of the high priority interrupt. This means that SVCALL interrupt processing can defer the high priority interrupt and result in the jitter in that interrupt response. Fix is to raise the priority of the high priority interrupt above the priority of the SVCALL interrupt. Suggested by Nathan Hartman.	2019-08-09 07:07:16 -06:00
spinlock.h	i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region.	2016-11-26 12:04:02 -06:00
syscall.h	arch/arm/src/include/xxx/syscall.h: Align semi-hosting call style with other syscalls	2019-01-26 07:40:47 -06:00