c4a13281a2
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3388 42af7a65-404d-4744-a932-0658087f49c3
263 lines
7.4 KiB
C
Executable File
263 lines
7.4 KiB
C
Executable File
/****************************************************************************
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* arch/x86/include/i486/irq.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_X86_INCLUDE_I486_IRQ_H
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#define __ARCH_X86_INCLUDE_I486_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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# include <arch/arch.h>
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#endif
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* ISR and IRQ numbers */
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#define ISR0 0
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#define ISR1 1
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#define ISR2 2
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#define ISR3 3
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#define ISR4 4
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#define ISR5 5
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#define ISR6 6
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#define ISR7 7
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#define ISR8 8
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#define ISR9 9
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#define ISR10 10
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#define ISR11 11
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#define ISR12 12
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#define ISR13 13
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#define ISR14 14
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#define ISR15 15
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#define ISR16 16
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#define ISR17 17
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#define ISR18 18
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#define ISR19 19
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#define ISR20 20
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#define ISR21 21
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#define ISR22 22
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#define ISR23 23
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#define ISR24 24
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#define ISR25 25
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#define ISR26 26
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#define ISR27 27
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#define ISR28 28
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#define ISR29 29
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#define ISR30 30
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#define ISR31 31
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#define IRQ0 32
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#define IRQ1 33
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#define IRQ2 34
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#define IRQ3 35
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#define IRQ4 36
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#define IRQ5 37
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#define IRQ6 38
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#define IRQ7 39
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#define IRQ8 40
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#define IRQ9 41
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#define IRQ10 42
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#define IRQ11 43
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#define IRQ12 44
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#define IRQ13 45
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#define IRQ14 46
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#define IRQ15 47
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#define NR_IRQS 48
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/* Common register save structgure created by up_saveusercontext() and by
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* ISR/IRQ interrupt processing.
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*/
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#define REG_DS (0) /* Data segment selector */
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#define REG_EDI (1) /* Saved by pusha */
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#define REG_ESI (2) /* " " "" " " */
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#define REG_EBP (3) /* " " "" " " */
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#define REG_ESP (4) /* " " "" " " (NOTE 1)*/
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#define REG_EBX (5) /* " " "" " " */
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#define REG_EDX (6) /* " " "" " " */
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#define REG_ECX (7) /* " " "" " " */
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#define REG_EAX (8) /* " " "" " " */
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#define REG_IRQNO (9) /* Interrupt number (NOTE 2) */
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#define REG_ERRCODE (10) /* Error code (NOTE 2) */
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#define REG_EIP (11) /* Pushed by process on interrupt processing */
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#define REG_CS (12) /* " " "" " " "" " " " " */
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#define REG_EFLAGS (13) /* " " "" " " "" " " " " */
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#define REG_SP (14) /* " " "" " " "" " " " " */
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#define REG_SS (15) /* " " "" " " "" " " " " */
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/* NOTE 1: Two versions of the ESP are saved: One from the interrupt
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* processing and one from pusha. Only the interrupt ESP (REG_SP) is used.
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* NOTE 2: This is not really state data. Rather, this is just a convenient
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* way to pass parameters from the interrupt handler to C cod.
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*/
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#define XCPTCONTEXT_REGS (16)
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#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* This struct defines the way the registers are stored */
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#ifndef __ASSEMBLY__
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struct xcptcontext
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{
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/* The following function pointer is non-zero if there are pending signals
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* to be processed.
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*/
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#ifndef CONFIG_DISABLE_SIGNALS
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void *sigdeliver; /* Actual type is sig_deliver_t */
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/* These are saved copies of instruction pointer and EFLAGS used during
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* signal processing.
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*/
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uint32_t saved_eip;
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uint32_t saved_eflags;
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#endif
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/* Register save area */
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uint32_t regs[XCPTCONTEXT_REGS];
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};
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* Get the current FLAGS register contents */
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static inline irqstate_t irqflags()
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{
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irqstate_t flags;
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asm volatile(
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"\tpushf\n"
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"\tpop %0\n"
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: "=rm" (flags)
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:
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: "memory");
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return flags;
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}
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/* Get a sample of the FLAGS register, determine if interrupts are disabled.
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* If the X86_FLAGS_IF is cleared by cli, then interrupts are disabled. If
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* if the X86_FLAGS_IF is set by sti, then interrupts are enable.
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*/
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static inline bool irqdisabled(irqstate_t flags)
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{
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return ((flags & X86_FLAGS_IF) == 0);
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}
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static inline bool irqenabled(irqstate_t flags)
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{
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return ((flags & X86_FLAGS_IF) != 0);
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}
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/* Disable interrupts unconditionally */
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static inline void irqdisable(void)
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{
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asm volatile("cli": : :"memory");
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}
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/* Enable interrupts unconditionally */
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static inline void irqenable(void)
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{
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asm volatile("sti": : :"memory");
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}
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/* Disable interrupts, but return previous interrupt state */
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static inline irqstate_t irqsave(void)
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{
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irqstate_t flags = irqflags();
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irqdisable();
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return flags;
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}
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/* Conditionally disable interrupts */
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static inline void irqrestore(irqstate_t flags)
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{
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if (irqenabled(flags))
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{
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irqenable();
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}
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}
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_X86_INCLUDE_I486_IRQ_H */
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