eeedce32c4
updates for arch: arm: cxd56xx:
* arch: arm: cxd56xx: add pinconfig
Add the HW pin configuration for cxd56xx
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add GPIO support
Add GPIO support for cxd56xx
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add support for GPIO interrupts
add support for GPIO interrupts
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add clock support
Add clock support for cxd56xx
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add PMIC support
Add support for PMIC (Power management integrated circuit)
for cxd56xx chip
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add FIFO CPU schedulier
add a simple FIFO schedulier that minimizes overhead
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add ICC support
add Inter Core Communication for cxd56xx
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
152 lines
5.8 KiB
C
152 lines
5.8 KiB
C
/****************************************************************************
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* arch/arm/include/cxd56xx/pin.h
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*
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* Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Copyright 2018 Sony Semiconductor Solutions Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
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* the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_CXD56XX_PIN_H
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#define __ARCH_ARM_INCLUDE_CXD56XX_PIN_H
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/****************************************************************************
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* Included Files
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***************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Pin number Definitions */
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#define PIN_RTC_CLK_IN (0)
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/* SYS GPIO: system power domain GPIOs */
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#define PIN_I2C4_BCK (1)
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#define PIN_I2C4_BDT (2)
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#define PIN_PMIC_INT (3)
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#define PIN_RTC_IRQ_OUT (4)
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#define PIN_AP_CLK (5)
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#define PIN_GNSS_1PPS_OUT (6)
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#define PIN_SPI0_CS_X (17)
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#define PIN_SPI0_SCK (18)
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#define PIN_SPI0_MOSI (19)
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#define PIN_SPI0_MISO (20)
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#define PIN_SPI1_CS_X (21)
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#define PIN_SPI1_SCK (22)
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#define PIN_SPI1_IO0 (23)
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#define PIN_SPI1_IO1 (24)
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#define PIN_SPI1_IO2 (25)
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#define PIN_SPI1_IO3 (26)
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#define PIN_SPI2_CS_X (27)
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#define PIN_SPI2_SCK (28)
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#define PIN_SPI2_MOSI (29)
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#define PIN_SPI2_MISO (30)
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#define PIN_HIF_IRQ_OUT (31)
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#define PIN_HIF_GPIO0 (32)
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#define PIN_SEN_IRQ_IN (37)
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#define PIN_SPI3_CS0_X (38)
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#define PIN_SPI3_CS1_X (39)
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#define PIN_SPI3_CS2_X (40)
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#define PIN_SPI3_SCK (41)
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#define PIN_SPI3_MOSI (42)
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#define PIN_SPI3_MISO (43)
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#define PIN_I2C0_BCK (44)
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#define PIN_I2C0_BDT (45)
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#define PIN_PWM0 (46)
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#define PIN_PWM1 (47)
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#define PIN_PWM2 (48)
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#define PIN_PWM3 (49)
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/* APP GPIO: application power domain GPIOs */
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#define PIN_IS_CLK (56)
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#define PIN_IS_VSYNC (57)
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#define PIN_IS_HSYNC (58)
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#define PIN_IS_DATA0 (59)
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#define PIN_IS_DATA1 (60)
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#define PIN_IS_DATA2 (61)
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#define PIN_IS_DATA3 (62)
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#define PIN_IS_DATA4 (63)
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#define PIN_IS_DATA5 (64)
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#define PIN_IS_DATA6 (65)
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#define PIN_IS_DATA7 (66)
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#define PIN_UART2_TXD (67)
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#define PIN_UART2_RXD (68)
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#define PIN_UART2_CTS (69)
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#define PIN_UART2_RTS (70)
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#define PIN_SPI4_CS_X (71)
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#define PIN_SPI4_SCK (72)
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#define PIN_SPI4_MOSI (73)
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#define PIN_SPI4_MISO (74)
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#define PIN_EMMC_CLK (75)
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#define PIN_SPI5_SCK (PIN_EMMC_CLK)
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#define PIN_EMMC_CMD (76)
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#define PIN_SPI5_CS_X (PIN_EMMC_CMD)
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#define PIN_EMMC_DATA0 (77)
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#define PIN_SPI5_MOSI (PIN_EMMC_DATA0)
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#define PIN_EMMC_DATA1 (78)
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#define PIN_SPI5_MISO (PIN_EMMC_DATA1)
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#define PIN_EMMC_DATA2 (79)
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#define PIN_EMMC_DATA3 (80)
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#define PIN_SDIO_CLK (81)
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#define PIN_SDIO_CMD (82)
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#define PIN_SDIO_DATA0 (83)
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#define PIN_SDIO_DATA1 (84)
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#define PIN_SDIO_DATA2 (85)
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#define PIN_SDIO_DATA3 (86)
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#define PIN_SDIO_CD (87)
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#define PIN_SDIO_WP (88)
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#define PIN_SDIO_CMDDIR (89)
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#define PIN_SDIO_DIR0 (90)
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#define PIN_SDIO_DIR1_3 (91)
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#define PIN_SDIO_CLKI (92)
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#define PIN_I2S0_BCK (93)
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#define PIN_I2S0_LRCK (94)
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#define PIN_I2S0_DATA_IN (95)
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#define PIN_I2S0_DATA_OUT (96)
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#define PIN_I2S1_BCK (97)
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#define PIN_I2S1_LRCK (98)
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#define PIN_I2S1_DATA_IN (99)
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#define PIN_I2S1_DATA_OUT (100)
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#define PIN_MCLK (101)
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#define PIN_PDM_CLK (102)
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#define PIN_PDM_IN (103)
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#define PIN_PDM_OUT (104)
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#define PIN_USB_VBUSINT (105)
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#endif /* __ARCH_ARM_INCLUDE_CXD56XX_PIN_H */
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