129 lines
6.8 KiB
C
129 lines
6.8 KiB
C
/****************************************************************************
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* arch/arm/src/str71x/str71x_rccu.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H
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#define __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "str71x_map.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Reset and Clock Control Unit (RCCU) register offsets *********************/
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/* All registers are 32-bits wide, but with the top 16 bits "reserved" */
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#define STR71X_RCCU_CCR_OFFSET (0x0000) /* 32-bits wide */
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#define STR71X_RCCU_CFR_OFFSET (0x0008) /* 32-bits wide */
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#define STR71X_RCCU_PLL1CR_OFFSET (0x0018) /* 32-bits wide */
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#define STR71X_RCCU_PER_OFFSET (0x001c) /* 32-bits wide */
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#define STR71X_RCCU_SMR_OFFSET (0x0020) /* 32-bits wide */
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/* Reset and Clock Control Unit (RCCU) register addresses *******************/
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#define STR71X_RCCU_CCR (STR71X_RCCU_BASE + STR71X_RCCU_CCR_OFFSET)
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#define STR71X_RCCU_CFR (STR71X_RCCU_BASE + STR71X_RCCU_CFR_OFFSET)
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#define STR71X_RCCU_PLL1CR (STR71X_RCCU_BASE + STR71X_RCCU_PLL1CR_OFFSET)
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#define STR71X_RCCU_PER (STR71X_RCCU_BASE + STR71X_RCCU_PER_OFFSET)
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#define STR71X_RCCU_SMR (STR71X_RCCU_BASE + STR71X_RCCU_SMR_OFFSET)
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/* Register bit settings ****************************************************/
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/* RCCU CCR register bit definitions */
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#define STR71X_RCCUCCR_LPOWFI (0x00000001) /* Bit 0: Low power mode in wait-for-interrupt mode */
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#define STR71X_RCCUCCR_WFICLKSEL (0x00000002) /* Bit 1: WFI clock select */
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#define STR71X_RCCUCCR_CKAFSEL (0x00000004) /* Bit 2: Alternate function clock select */
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#define STR71X_RCCUCCR_SRESEN (0x00000008) /* Bit 3: Software reset enable */
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#define STR71X_RCCUCCR_ENCLOCK (0x00000080) /* Bit 7: Lock interrupt enable */
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#define STR71X_RCCUCCR_ENCKAF (0x00000100) /* Bit 8: CKAF interrupt enable */
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#define STR71X_RCCUCCR_ENCK216 (0x00000200) /* Bit 9: CK2_16 interrupt enable */
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#define STR71X_RCCUCCR_ENSTOP (0x00000400) /* Bit 10: Stop interrupt enable */
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#define STR71X_RCCUCCR_ENHALT (0x00000800) /* Bit 11: Enable halt */
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/* RCCU CFR register bit definitions */
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#define STR71X_RCCUCFR_CSUCKSEL (0x00000001) /* Bit 0: CSU clock select */
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#define STR71X_RCCUCFR_LOCK (0x00000002) /* Bit 1: PLL locked-in */
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#define STR71X_RCCUCFR_CKAFST (0x00000004) /* Bit 2: CK_AF status */
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#define STR71X_RCCUCFR_CK216 (0x00000008) /* Bit 3: CLK2/16 selection */
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#define STR71X_RCCUCFR_CKSTOPEN (0x00000010) /* Bit 4: Clock stop enable */
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#define STR71X_RCCUCFR_SOFTRES (0x00000020) /* Bit 5: Software reset */
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#define STR71X_RCCUCFR_WDGRES (0x00000040) /* Bit 6: Watchdog reset */
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#define STR71X_RCCUCFR_RTCALARM (0x00000080) /* Bit 7: RTC alarm reset */
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#define STR71X_RCCUCFR_LVDRES (0x00000200) /* Bit 9: Voltage regulator low voltage detector reset */
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#define STR71X_RCCUCFR_WKPRES (0x00000400) /* Bit 10: External wakeup */
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#define STR71X_RCCUCFR_LOCKI (0x00000800) /* Bit 11: Lock interrupt pending */
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#define STR71X_RCCUCFR_CKAFI (0x00001000) /* Bit 12: CK_AF switching interrupt pending */
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#define STR71X_RCCUCFR_CK216I (0x00002000) /* Bit 13: CK2_16 switching interrupt pending */
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#define STR71X_RCCUCFR_STOPI (0x00004000) /* Bit 14: Stop interrupt pending */
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#define STR71X_RCCUCFR_DIV2 (0x00008000) /* Bit 15: OSCIN divided by 2 */
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/* RCCU PPL1CR register bit definitions */
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#define STR71X_RCCUPLL1CR_DXMASK (0x00000003) /* Bit 0-2: PLL1 clock divisor */
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#define STR71X_RCCUPLL1CR_DIV1 (0x00000000) /* PLLCK / 1 */
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#define STR71X_RCCUPLL1CR_DIV2 (0x00000001) /* PLLCK / 2 */
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#define STR71X_RCCUPLL1CR_DIV3 (0x00000002) /* PLLCK / 3 */
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#define STR71X_RCCUPLL1CR_DIV4 (0x00000003) /* PLLCK / 4 */
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#define STR71X_RCCUPLL1CR_DIV5 (0x00000004) /* PLLCK / 5 */
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#define STR71X_RCCUPLL1CR_DIV6 (0x00000005) /* PLLCK / 6 */
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#define STR71X_RCCUPLL1CR_DIV7 (0x00000006) /* PLLCK / 7 */
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#define STR71X_RCCUPLL1CR_CLK2 (0x00000007) /* FREEN==0: CLK2 */
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#define STR71X_RCCUPLL1CR_FREERM (0x00000007) /* FREEN==1: PLL1 in free running mode */
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#define STR71X_RCCUPLL1CR_MXMASK (0x00000030) /* Bit 4-5: PLL1 clock multiplier */
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#define STR71X_RCCUPLL1CR_MUL20 (0x00000000) /* CLK2 * 20 */
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#define STR71X_RCCUPLL1CR_MUL12 (0x00000010) /* CLK2 * 12 */
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#define STR71X_RCCUPLL1CR_MUL24 (0x00000020) /* CLK2 * 24 */
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#define STR71X_RCCUPLL1CR_MUL16 (0x00000030) /* CLK2 * 16 */
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#define STR71X_RCCUPLL1CR_FREFRANGE (0x00000040) /* Bit 6: Reference frequency range select */
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#define STR71X_RCCUPLL1CR_FREEN (0x00000080) /* Bit 7: PKL free running mode */
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/* RCCU PER register bit definitions */
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#define STR71X_RCCUPER_EMI (0x00000004) /* Bit 2: EMI */
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#define STR71X_RCCUPER_USBKERNEL (0x00000010) /* Bit 4: USB Kernel */
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/* RCCU SMR register bit definitions */
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#define STR71X_RCCUSMR_WFI (0x00000001) /* Bit 0: Wait for interrupt */
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#define STR71X_RCCUSMR_HALT (0x00000000) /* Bit 1: Halt */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_STR71X_STR71X_RCCU_H */
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