185 lines
6.1 KiB
C
185 lines
6.1 KiB
C
/****************************************************************************
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* arch/arm/src/str71x/str71x_timerisr.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <time.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "clock/clock.h"
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#include "arm_internal.h"
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#include "str71x.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* The desired timer interrupt frequency is provided by the definition
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* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
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* system clock ticks per second. That value is a user configurable setting
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* that defaults to 100 (100 ticks per second = 10 MS interval).
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*
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* The best accuracy would be obtained by using the largest value in the
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* the output compare register (OCAR), i.e., 0xffff = 65,535:
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*/
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#define MAX_OCAR 65535
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/* In this case, the desired, maximum clocking would be MAX_TIM0CLK. For
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* example if CLK_TCK is the default of 100Hz, then the ideal clocking for
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* timer0 would be 6,553,500
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*/
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#define MAX_TIM0CLK (MAX_OCAR * CLK_TCK)
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/* The best divider then would be the one that reduces PCLK2 to MAX_TIM0CLK.
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* Note that the following calculation forces an integer divisor to the next
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* integer above the optimal. So, for example, if MAX_TIM0CLK is 6,553,500
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* and PCLK2 is 32MHz, then ideal PCLK2_DIVIDER would be 4.88 but 5 is used
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* instead. The value 5 would give an actual TIM0CLK of 6,400,000, less
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* than the maximum.
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*/
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#if STR71X_PCLK2 > MAX_TIM0CLK
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# define PCLK2_DIVIDER (((STR71X_PCLK2) + (MAX_TIM0CLK+1)) / MAX_TIM0CLK)
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#else
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# define PCLK2_DIVIDER (1)
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#endif
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#if PCLK2_DIVIDER > 255
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# error "PCLK2 is too fast for any divisor"
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#endif
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/* Then we can get the actual OCAR value from the selected divider value.
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* For example, if PCLK2 is 32MHz and PCLK2_DIVIDER is 5, then the actual
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* TIM0CLK would 6,4000,000 and the final OCAR_VALUE would be 64,000.
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*/
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#define ACTUAL_TIM0CLK (STR71X_PCLK2 / PCLK2_DIVIDER)
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#define OCAR_VALUE (ACTUAL_TIM0CLK / CLK_TCK)
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#if OCAR_VALUE > 65535
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# error "PCLK2 is too fast for the configured CLK_TCK"
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Function: str71x_timerisr
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*
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* Description:
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* The timer ISR will perform a variety of services for various portions
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* of the systems.
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*
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****************************************************************************/
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static int str71x_timerisr(int irq, uint32_t *regs, void *arg)
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{
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uint16_t ocar;
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/* Clear all the output compare A interrupt status bit */
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putreg16(~STR71X_TIMERSR_OCFA, STR71X_TIMER0_SR);
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/* Set up for the next compare match. We could either reset
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* the OCAR and CNTR to restart, or simply update the OCAR as
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* follows to that the match occurs later without resetting:
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*/
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ocar = getreg16(STR71X_TIMER0_OCAR);
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ocar += OCAR_VALUE;
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putreg16(ocar, STR71X_TIMER0_OCAR);
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/* Process timer interrupt */
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nxsched_process_timer();
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return 0;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Function: up_timer_initialize
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*
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* Description:
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* This function is called during start-up to initialize
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* the timer interrupt.
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*
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****************************************************************************/
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void up_timer_initialize(void)
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{
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irqstate_t flags;
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/* Make sure that timer0 is disabled */
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flags = enter_critical_section();
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putreg16(0x0000, STR71X_TIMER0_CR1);
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putreg16(0x0000, STR71X_TIMER0_CR2);
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putreg16(0x0000, STR71X_TIMER0_SR);
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/* Configure TIM0 so that it is clocked by the internal APB2 frequency
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* (PCLK2) divided by the above prescaler value (1) -- versus an external
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* Clock.
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* -- Nothing to do because STR71X_TIMERCR1_ECKEN is already cleared.
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*
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* Select a divisor to reduce the frequency of clocking.
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* This must be done so that the entire timer interval can fit in the
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* 16-bit OCAR register. (see the discussion above).
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*/
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putreg16(STR71X_TIMERCR2_OCAIE | (PCLK2_DIVIDER - 1), STR71X_TIMER0_CR2);
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/* Start The TIM0 Counter and enable the output comparison A */
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putreg16(STR71X_TIMERCR1_EN | STR71X_TIMERCR1_OCAE, STR71X_TIMER0_CR1);
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/* Setup output compare A for desired interrupt frequency. Note that
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* the OCAE and OCBE bits are cleared and the pins are available for other
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* functions.
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*/
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putreg16(OCAR_VALUE, STR71X_TIMER0_OCAR);
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putreg16(0xfffc, STR71X_TIMER0_CNTR);
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/* Attach the timer interrupt vector */
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irq_attach(STR71X_IRQ_SYSTIMER, (xcpt_t)str71x_timerisr, NULL);
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/* And enable the timer interrupt */
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up_enable_irq(STR71X_IRQ_SYSTIMER);
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leave_critical_section(flags);
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}
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