f6695738e1
Basic work required for uniprocessor CortexR52 (ARMv8R AARCH32) using GICv3 and CP15 mapped arch timer. Tested on ARM FVP 11.20. Port is based on ARMv8R AARCH64 and ARMv7R code. Excuse possible copy-paste leftovers.
152 lines
5.6 KiB
C
152 lines
5.6 KiB
C
/****************************************************************************
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* arch/arm/src/armv8-r/arm.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* References:
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*
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* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
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* Copyright 1996-1998, 2000, 2004-2012 ARM.
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* All rights reserved. ARM DDI 0406C.c (ID051414)
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*/
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#ifndef __ARCH_ARM_SRC_ARMV8_R_ARM_H
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#define __ARCH_ARM_SRC_ARMV8_R_ARM_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ASSEMBLY__
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# include <nuttx/compiler.h>
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define BIT(n) ((1UL) << (n))
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#define BIT64(n) ((1ULL) << (n))
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/* Bit mask with bits 0 through n-1 (inclusive) set,
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* or 0 if n is 0.
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*/
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#define BIT_MASK(n) (BIT(n) - 1)
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#define BIT64_MASK(n) (BIT64(n) - 1ULL)
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/* ARMv8-R ******************************************************************/
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/* PSR bits */
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#define PSR_MODE_SHIFT (0) /* Bits 0-4: Mode fields */
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#define PSR_MODE_MASK (31 << PSR_MODE_SHIFT)
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# define PSR_MODE_USR (16 << PSR_MODE_SHIFT) /* User mode */
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# define PSR_MODE_FIQ (17 << PSR_MODE_SHIFT) /* FIQ mode */
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# define PSR_MODE_IRQ (18 << PSR_MODE_SHIFT) /* IRQ mode */
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# define PSR_MODE_SVC (19 << PSR_MODE_SHIFT) /* Supervisor mode */
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# define PSR_MODE_ABT (23 << PSR_MODE_SHIFT) /* Abort mode */
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# define PSR_MODE_HYP (26 << PSR_MODE_SHIFT) /* Hypervisor mode */
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# define PSR_MODE_UND (27 << PSR_MODE_SHIFT) /* Undefined mode */
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# define PSR_MODE_SYS (31 << PSR_MODE_SHIFT) /* System mode */
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#define PSR_T_BIT (1 << 5) /* Bit 5: Thumb execution state bit */
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#define PSR_MASK_SHIFT (6) /* Bits 6-8: Mask Bits */
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#define PSR_MASK_MASK (7 << PSR_GE_SHIFT)
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# define PSR_F_BIT (1 << 6) /* Bit 6: FIQ mask bit */
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# define PSR_I_BIT (1 << 7) /* Bit 7: IRQ mask bit */
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# define PSR_A_BIT (1 << 8) /* Bit 8: Asynchronous abort mask */
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#define PSR_E_BIT (1 << 9) /* Bit 9: Endianness execution state bit */
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#define PSR_IT27_SHIFT (10) /* Bits 10-15: If-Then execution state bits IT[2:7] */
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#define PSR_IT27_MASK (0x3f << PSR_IT27_SHIFT)
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#define PSR_GE_SHIFT (16) /* Bits 16-19: Greater than or Equal flags */
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#define PSR_GE_MASK (15 << PSR_GE_SHIFT)
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/* Bits 20-23: Reserved. RAZ/SBZP */
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#define PSR_J_BIT (1 << 24) /* Bit 24: Jazelle state bit */
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#define PSR_IT01_SHIFT (25) /* Bits 25-26: If-Then execution state bits IT[0:1] */
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#define PSR_IT01_MASK (3 << PSR_IT01_SHIFT)
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#define PSR_Q_BIT (1 << 27) /* Bit 27: Cumulative saturation bit */
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#define PSR_V_BIT (1 << 28) /* Bit 28: Overflow condition flag */
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#define PSR_C_BIT (1 << 29) /* Bit 29: Carry condition flag */
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#define PSR_Z_BIT (1 << 30) /* Bit 30: Zero condition flag */
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#define PSR_N_BIT (1 << 31) /* Bit 31: Negative condition flag */
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Name: arm_boot
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*
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* Description:
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* Complete boot operations started in arm_head.S
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*
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* Boot Sequence
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*
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* 1. The __start entry point in armv8-r/arm_head.S is invoked upon power-
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* on reset.
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* 2. __start prepares CPU for code execution.
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*
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****************************************************************************/
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void arm_boot(void);
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/****************************************************************************
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* Name: arm_data_initialize
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*
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* Description:
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* Clear all of .bss to zero; set .data to the correct initial values.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void arm_data_initialize(void);
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_ARMV8_R_ARM_H */
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