367 lines
10 KiB
C
367 lines
10 KiB
C
/****************************************************************************
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* arch/arm/src/armv7-a/arm_mmu.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include "cp15_cacheops.h"
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#include "mmu.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: mmu_l1_setentry
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*
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* Description:
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* Set a one level 1 translation table entry. Only a single L1 page table
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* is supported.
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*
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* Input Parameters:
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* paddr - The physical address to be mapped. Must be aligned to a 1MB
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* address boundary
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* vaddr - The virtual address to be mapped. Must be aligned to a 1MB
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* address boundary
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* mmuflags - The MMU flags to use in the mapping.
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*
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****************************************************************************/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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void mmu_l1_setentry(uint32_t paddr, uint32_t vaddr, uint32_t mmuflags)
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{
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uint32_t *l1table = mmu_l1_pgtable();
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uint32_t index = vaddr >> 20;
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/* Save the page table entry */
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l1table[index] = (paddr | mmuflags);
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/* Flush the data cache entry. Make sure that the modified contents
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* of the page table are flushed into physical memory.
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*/
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cp15_clean_dcache_bymva((uint32_t)&l1table[index]);
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/* Invalidate the TLB cache associated with virtual address range */
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mmu_invalidate_region(vaddr, SECTION_SIZE);
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}
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#endif
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/****************************************************************************
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* Name: mmu_l1_restore
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*
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* Description:
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* Restore one L1 table entry previously returned by mmu_l1_getentry() (or
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* any other encoded L1 page table value).
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*
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* Input Parameters:
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* vaddr - A virtual address to be mapped
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* l1entry - The value to write into the page table entry
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*
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****************************************************************************/
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#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_ADDRENV)
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void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry)
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{
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uint32_t *l1table = mmu_l1_pgtable();
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uint32_t index = vaddr >> 20;
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/* Set the encoded page table entry */
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l1table[index] = l1entry;
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/* Flush the data cache entry. Make sure that the modified contents
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* of the page table are flushed into physical memory.
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*/
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cp15_clean_dcache_bymva((uint32_t)&l1table[index]);
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/* Invalidate the TLB cache associated with virtual address range */
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mmu_invalidate_region(vaddr & PMD_PTE_PADDR_MASK, SECTION_SIZE);
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}
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#endif
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/****************************************************************************
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* Name: mmu_l2_setentry
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*
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* Description:
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* Set one small (4096B) entry in a level2 translation table.
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*
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* Input Parameters:
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* l2vaddr - the virtual address of the beginning of the L2 translation
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* table.
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* paddr - The physical address to be mapped. Must be aligned to a 4KB
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* address boundary
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* vaddr - The virtual address to be mapped. Must be aligned to a 4KB
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* address boundary
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* mmuflags - The MMU flags to use in the mapping.
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*
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****************************************************************************/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr,
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uint32_t mmuflags)
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{
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uint32_t *l2table = (uint32_t *)l2vaddr;
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uint32_t index;
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/* The table divides a 1Mb address space up into 256 entries, each
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* corresponding to 4Kb of address space. The page table index is
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* related to the offset from the beginning of 1Mb region.
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*/
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index = (vaddr & 0x000ff000) >> 12;
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/* Save the table entry */
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l2table[index] = (paddr | mmuflags);
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/* Flush the data cache entry. Make sure that the modified contents
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* of the page table are flushed into physical memory.
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*/
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cp15_clean_dcache_bymva((uint32_t)&l2table[index]);
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/* Invalidate the TLB cache associated with virtual address range */
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cp15_invalidate_tlb_bymva(vaddr);
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}
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#endif
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/****************************************************************************
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* Name: mmu_l1_map_region
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*
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* Description:
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* Set multiple level 1 translation table entries in order to map a
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* region of memory.
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*
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* Input Parameters:
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* mapping - Describes the mapping to be performed.
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*
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****************************************************************************/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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void mmu_l1_map_region(const struct section_mapping_s *mapping)
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{
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uint32_t paddr = mapping->physbase;
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uint32_t vaddr = mapping->virtbase;
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uint32_t mmuflags = mapping->mmuflags;
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int i;
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/* Loop, writing each mapping into the L1 page table */
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for (i = 0; i < mapping->nsections; i++)
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{
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mmu_l1_setentry(paddr, vaddr, mmuflags);
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paddr += SECTION_SIZE;
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vaddr += SECTION_SIZE;
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}
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}
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#endif
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/****************************************************************************
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* Name: mmu_l1_map_regions
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*
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* Description:
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* Set multiple level 1 translation table entries in order to map a region
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* array of memory.
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*
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* Input Parameters:
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* mappings - Describes the array of mappings to be performed.
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* count - The number of mappings to be performed.
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*
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****************************************************************************/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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void mmu_l1_map_regions(const struct section_mapping_s *mappings,
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size_t count)
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{
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size_t i;
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for (i = 0; i < count; i++)
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{
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mmu_l1_map_region(&mappings[i]);
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}
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}
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#endif
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/****************************************************************************
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* Name: mmu_l1_map_page
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*
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* Description:
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* Set level 1 page entrie in order to map a region
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* array of memory.
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*
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* Input Parameters:
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* mapping - Describes the mapping to be performed.
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*
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****************************************************************************/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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void mmu_l1_map_page(const struct section_mapping_s *mapping)
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{
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uint32_t virtaddr = mapping->virtbase;
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uint32_t l2table = mapping->physbase;
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uint32_t i;
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for (i = 0; i < mapping->nsections; i++)
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{
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mmu_l1_setentry(l2table, virtaddr, mapping->mmuflags);
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/* Update the L2 page table address for the next L1 table entry. */
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virtaddr += SECTION_SIZE;
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l2table += 1024;
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}
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}
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#endif
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/****************************************************************************
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* Name: mmu_l1_map_pages
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*
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* Description:
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* Set multiple level 1 page entries in order to map a region
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* array of memory.
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*
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* Input Parameters:
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* mappings - Describes the mapping to be performed.
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* count - The number of mappings to be performed.
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*
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****************************************************************************/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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void mmu_l1_map_pages(const struct section_mapping_s *mappings,
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size_t count)
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{
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size_t i;
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for (i = 0; i < count; i++)
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{
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mmu_l1_map_page(&mappings[i]);
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}
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}
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#endif
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/****************************************************************************
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* Name: mmu_l2_map_page
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*
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* Description:
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* Set level 2 page entrie in order to map a region
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* array of memory.
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*
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* Input Parameters:
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* mapping - Describes the mapping to be performed.
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*
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****************************************************************************/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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void mmu_l2_map_page(const struct page_mapping_s *mapping)
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{
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uint32_t l2table = mapping->l2table;
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struct page_entry_s *entry;
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uint32_t paddr;
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uint32_t vaddr;
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uint32_t entry_cnt;
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uint32_t page_cnt;
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for (entry_cnt = 0; entry_cnt < mapping->entrynum; entry_cnt++)
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{
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entry = (struct page_entry_s *)&mapping->entry[entry_cnt];
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paddr = entry->physbase;
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vaddr = entry->virtbase;
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for (page_cnt = 0; page_cnt < entry->npages; page_cnt++)
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{
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mmu_l2_setentry(l2table, paddr, vaddr, entry->mmuflags);
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paddr += 4096;
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vaddr += 4096;
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if ((vaddr & 0x000ff000) == 0)
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{
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l2table += 1024;
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}
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}
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}
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}
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#endif
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/****************************************************************************
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* Name: mmu_l2_map_pages
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*
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* Description:
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* Set multiple level 2 page entries in order to map a region
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* array of memory.
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*
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* Input Parameters:
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* mappings - Describes the mapping to be performed.
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* count - The number of mappings to be performed.
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*
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****************************************************************************/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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void mmu_l2_map_pages(const struct page_mapping_s *mappings,
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size_t count)
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{
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size_t i;
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for (i = 0; i < count; i++)
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{
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mmu_l2_map_page(&mappings[i]);
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}
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}
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#endif
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/****************************************************************************
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* Name: mmu_invalidate_region
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*
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* Description:
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* Invalidate TLBs for a range of addresses (all 4KB aligned).
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*
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* Input Parameters:
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* vaddr - The beginning of the region to invalidate.
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* size - The size of the region in bytes to be invalidated.
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*
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****************************************************************************/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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void mmu_invalidate_region(uint32_t vstart, size_t size)
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{
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uint32_t vaddr = vstart & 0xfffff000;
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uint32_t vend = vstart + size;
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/* Loop, invalidating regions */
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while (vaddr < vend)
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{
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cp15_invalidate_tlb_bymva(vaddr);
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vaddr += 4096;
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}
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}
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#endif
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