Huang Qi c6942b68d5 arch/risc-v: Add handler for misaligned load/store ... Some risc-v based chips don't support unaligned data access, it will trigger a exception and then lead to crash. In this patch, we handle the misaligned access by software to make system run continue. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>		2022-04-08 23:27:07 +08:00
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include	esp32c3: Simplify irq dispatch logic	2022-04-07 18:16:35 +02:00
src	arch/risc-v: Add handler for misaligned load/store	2022-04-08 23:27:07 +08:00
Kconfig	RISC-V: Implement skeleton for a per CPU structure	2022-04-01 16:19:42 -03:00