nuttx/boards/risc-v/mpfs/icicle
Eero Nurkkala 8e43f39141 mpfs: cache: provide L1/L2 cache enablers
E51 may configure the L1 and L2 caches. Once configured,
no reconfiguration is possible after hardware reset is
issued.

L2 is 16-way set associative with write-back policy. The
size 2 MB, from which 1 MB is utilized with the values
provided here. That's a total of 8 ways. The rest of the
L2 is left out for the bootloader usage.

mpfs_enable_cache() first checks the bootloader usage
doesn't overlap with the cache itself, thus providing a
set of functional values.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2021-11-04 11:00:55 -03:00
..
configs mpfs/icicle/configs/hwtest: enable SD card 2021-09-18 12:18:09 -03:00
include mpfs: cache: provide L1/L2 cache enablers 2021-11-04 11:00:55 -03:00
kernel Rename LIB_ to LIBC_ for all libc Kconfig 2021-08-05 19:45:24 +02:00
scripts mpfs: board Make.defs: add bootloader linker option 2021-10-21 22:40:26 -05:00
src mpfs: emmcsd: add Kconfig/Makefile and board files 2021-09-18 12:18:09 -03:00
Kconfig add support for PolarFire SoC and icicle board 2021-05-24 22:55:44 -05:00