180 lines
8.8 KiB
C
180 lines
8.8 KiB
C
/****************************************************************************
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* arch/arm/src/kl/hardware/kl_i2c.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_I2C_H
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#define __ARCH_ARM_SRC_KL_HARDWARE_KL_I2C_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define KL_I2C_A1_OFFSET 0x0000 /* I2C Address Register 1 */
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#define KL_I2C_F_OFFSET 0x0001 /* I2C Frequency Divider register */
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#define KL_I2C_C1_OFFSET 0x0002 /* I2C Control Register 1 */
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#define KL_I2C_S_OFFSET 0x0003 /* I2C Status Register */
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#define KL_I2C_D_OFFSET 0x0004 /* I2C Data I/O register */
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#define KL_I2C_C2_OFFSET 0x0005 /* I2C Control Register 2 */
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#define KL_I2C_FLT_OFFSET 0x0006 /* I2C Programmable Input Glitch Filter register */
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#define KL_I2C_RA_OFFSET 0x0007 /* I2C Range Address register */
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#define KL_I2C_SMB_OFFSET 0x0008 /* I2C SMBus Control and Status register */
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#define KL_I2C_A2_OFFSET 0x0009 /* I2C Address Register 2 */
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#define KL_I2C_SLTH_OFFSET 0x000a /* I2C SCL Low Timeout Register High */
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#define KL_I2C_SLTL_OFFSET 0x000b /* I2C SCL Low Timeout Register Low */
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/* Register Addresses *******************************************************/
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#define KL_I2C0_A1 (KL_I2C0_BASE+KL_I2C_A1_OFFSET)
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#define KL_I2C0_F (KL_I2C0_BASE+KL_I2C_F_OFFSET)
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#define KL_I2C0_C1 (KL_I2C0_BASE+KL_I2C_C1_OFFSET)
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#define KL_I2C0_S (KL_I2C0_BASE+KL_I2C_S_OFFSET)
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#define KL_I2C0_D (KL_I2C0_BASE+KL_I2C_D_OFFSET)
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#define KL_I2C0_C2 (KL_I2C0_BASE+KL_I2C_C2_OFFSET)
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#define KL_I2C0_FLT (KL_I2C0_BASE+KL_I2C_FLT_OFFSET)
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#define KL_I2C0_RA (KL_I2C0_BASE+KL_I2C_RA_OFFSET)
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#define KL_I2C0_SMB (KL_I2C0_BASE+KL_I2C_SMB_OFFSET)
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#define KL_I2C0_A2 (KL_I2C0_BASE+KL_I2C_A2_OFFSET)
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#define KL_I2C0_SLTH (KL_I2C0_BASE+KL_I2C_SLTH_OFFSET)
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#define KL_I2C0_SLTL (KL_I2C0_BASE+KL_I2C_SLTL_OFFSET)
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#define KL_I2C1_A1 (KL_I2C1_BASE+KL_I2C_A1_OFFSET)
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#define KL_I2C1_F (KL_I2C1_BASE+KL_I2C_F_OFFSET)
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#define KL_I2C1_C1 (KL_I2C1_BASE+KL_I2C_C1_OFFSET)
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#define KL_I2C1_S (KL_I2C1_BASE+KL_I2C_S_OFFSET)
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#define KL_I2C1_D (KL_I2C1_BASE+KL_I2C_D_OFFSET)
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#define KL_I2C1_C2 (KL_I2C1_BASE+KL_I2C_C2_OFFSET)
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#define KL_I2C1_FLT (KL_I2C1_BASE+KL_I2C_FLT_OFFSET)
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#define KL_I2C1_RA (KL_I2C1_BASE+KL_I2C_RA_OFFSET)
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#define KL_I2C1_SMB (KL_I2C1_BASE+KL_I2C_SMB_OFFSET)
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#define KL_I2C1_A2 (KL_I2C1_BASE+KL_I2C_A2_OFFSET)
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#define KL_I2C1_SLTH (KL_I2C1_BASE+KL_I2C_SLTH_OFFSET)
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#define KL_I2C1_SLTL (KL_I2C1_BASE+KL_I2C_SLTL_OFFSET)
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/* Register Bit Definitions *************************************************/
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/* I2C Address Register 1 (8-bit) */
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/* Bit 0: Reserved */
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#define I2C_A1_SHIFT (1) /* Bits 1-7: Address */
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#define I2C_A1_MASK (0x7f << I2C_A1_SHIFT)
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/* I2C Frequency Divider register (8-bit) */
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#define I2C_F_ICR_SHIFT (0) /* Bits 0-5: Clock rate */
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#define I2C_F_ICR_MASK (0x3f << I2C_F_ICR_SHIFT)
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#define I2C_F_MULT_SHIFT (6) /* Bits 6-7: Multiplier factor */
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#define I2C_F_MULT_MASK (3 << I2C_F_MULT_SHIFT)
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# define I2C_F_MULT_1 (0 << I2C_F_MULT_SHIFT)
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# define I2C_F_MULT_2 (1 << I2C_F_MULT_SHIFT)
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# define I2C_F_MULT_4 (2 << I2C_F_MULT_SHIFT)
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/* I2C Control Register 1 (8-bit) */
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#define I2C_C1_DMAEN (1 << 0) /* Bit 0: DMA enable */
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#define I2C_C1_WUEN (1 << 1) /* Bit 1: Wakeup enable */
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#define I2C_C1_RSTA (1 << 2) /* Bit 2: Repeat START */
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#define I2C_C1_TXAK (1 << 3) /* Bit 3: Transmit acknowledge enable */
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#define I2C_C1_TX (1 << 4) /* Bit 4: Transmit mode select */
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#define I2C_C1_MST (1 << 5) /* Bit 5: Master mode select */
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#define I2C_C1_IICIE (1 << 6) /* Bit 6: I2C interrupt enable */
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#define I2C_C1_IICEN (1 << 7) /* Bit 7: I2C enable */
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/* I2C Status Register (8-bit) */
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#define I2C_S_RXAK (1 << 0) /* Bit 0: Receive acknowledge */
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#define I2C_S_IICIF (1 << 1) /* Bit 1: Interrupt flag */
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#define I2C_S_SRW (1 << 2) /* Bit 2: Slave read/write */
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#define I2C_S_RAM (1 << 3) /* Bit 3: Range address match */
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#define I2C_S_ARBL (1 << 4) /* Bit 4: Arbitration lost */
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#define I2C_S_BUSY (1 << 5) /* Bit 5: Bus busy */
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#define I2C_S_IAAS (1 << 6) /* Bit 6: Addressed as a slave */
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#define I2C_S_TCF (1 << 7) /* Bit 7: Transfer complete flag */
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/* I2C Data I/O register (8-bit data register) */
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/* I2C Control Register 2 (8-bit) */
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#define I2C_C2_AD_SHIFT (0) /* Bits 0-2: Slave address */
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#define I2C_C2_AD_MASK (7 << I2C_C2_AD_SHIFT)
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#define I2C_C2_RMEN (1 << 3) /* Bit 3: Range address matching enable */
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#define I2C_C2_SBRC (1 << 4) /* Bit 4: Slave baud rate control */
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#define I2C_C2_HDRS (1 << 5) /* Bit 5: High drive select */
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#define I2C_C2_ADEXT (1 << 6) /* Bit 6: Address extension */
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#define I2C_C2_GCAEN (1 << 7) /* Bit 7: General call address enable */
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/* I2C Programmable Input Glitch Filter register (8-bit) */
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/* Bits 5-7: Reserved */
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#define I2C_FLT_SHIFT (0) /* Bits 0-4: I2C programmable filter factor */
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#define I2C_FLT_MASK (0x1f << I2C_FLT_SHIFT)
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#define I2C_FLT_STOPIE (1 << 5) /* Bit 5: Stop interrupt enable */
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#define I2C_FLT_STOPF (1 << 6) /* Bit 6: Stop detect flag */
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#define I2C_FLT_SHEN (1 << 7) /* Bit 7: Stop hold enable */
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/* I2C Range Address register (8-bit) */
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/* Bit 0: Reserved */
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#define I2C_RA_SHIFT (1) /* Bits 1-7: Range slave address */
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#define I2C_RA_MASK (0x7f << I2C_RA_SHIFT)
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/* I2C SMBus Control and Status register (8-bit) */
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#define I2C_SMB_SHTF2IE (1 << 0) /* Bit 0: SHTF2 interrupt enable */
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#define I2C_SMB_SHTF2 (1 << 1) /* Bit 1: SCL high timeout flag 2 */
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#define I2C_SMB_SHTF1 (1 << 2) /* Bit 2: SCL high timeout flag 1 */
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#define I2C_SMB_SLTF (1 << 3) /* Bit 3: SCL low timeout flag */
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#define I2C_SMB_TCKSEL (1 << 4) /* Bit 4: Timeout counter clock select */
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#define I2C_SMB_SIICAEN (1 << 5) /* Bit 5: Second I2C address enable */
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#define I2C_SMB_ALERTEN (1 << 6) /* Bit 6: SMBus alert response address enable */
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#define I2C_SMB_FACK (1 << 7) /* Bit 7: Fast NACK/ACK enable */
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/* I2C Address Register 2 (8-bit) */
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/* Bit 0: Reserved */
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#define I2C_A2_SAD_SHIFT (1) /* Bits 1-7: SMBus address */
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#define I2C_A2_SAD_MASK (0x7f << I2C_A2_SHIFT)
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/* I2C SCL Low Timeout Register High/Low
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*(16-bit data in two 8-bit registers)
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*/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_I2C_H */
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