504 lines
16 KiB
C
504 lines
16 KiB
C
/****************************************************************************
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* arch/arm/src/s32k3xx/s32k3xx_pinirq.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Copyright 2022 NXP */
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <arch/board/board.h>
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#include <nuttx/config.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include "arm_internal.h"
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#include <s32k3xx_pin.h>
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#include <hardware/s32k3xx_siul2.h>
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#include <hardware/s32k3xx_wkpu.h>
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#ifdef CONFIG_S32K3XX_GPIOIRQ
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define EIRQ_IMCR_FIRST 528 /* First EIRQ IMCR index */
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#define EIRQ_IMCR_LAST 559 /* Last EIRQ IMCR index */
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#define WKPU_SRC_OFFSET 4 /* Wakeup Source 0-3 are internal sources */
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct s32k3xx_pinirq_s
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{
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xcpt_t handler;
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void *arg;
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* Interrupt vectors. To keep the memory usage at a minimum, the logic may
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* be configured per module.
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*/
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#ifdef CONFIG_S32K3XX_EIRQINTS
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static struct s32k3xx_pinirq_s g_eirqisrs[32];
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#endif
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#ifdef CONFIG_S32K3XX_WKPUINTS
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static struct s32k3xx_pinirq_s g_wkpuisrs[60];
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: s32k3xx_eirqinterrupt
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*
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* Description:
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* External Interrupt (EIRQ) interrupt handling.
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*
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****************************************************************************/
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#ifdef CONFIG_S32K3XX_EIRQINTS
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static int s32k3xx_eirqinterrupt(int irq, void *context, void *arg)
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{
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uint32_t disr0;
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uint32_t direr0;
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uint32_t eif;
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int i;
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/* Find interrupt flags for all enabled interrupts */
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disr0 = getreg32(S32K3XX_SIUL2_DISR0);
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direr0 = getreg32(S32K3XX_SIUL2_DIRER0);
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eif = disr0 & direr0;
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/* Examine each EIRQ channel */
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for (i = 0; (i < 32) && (eif != 0); i++)
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{
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uint32_t bit = (1 << i);
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if ((eif & bit) != 0)
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{
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if (g_eirqisrs[i].handler != NULL)
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{
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xcpt_t handler = g_eirqisrs[i].handler;
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void *argument = g_eirqisrs[i].arg;
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/* There is a registered interrupt handler... invoke it */
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handler(irq, context, argument);
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}
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/* Writing a one to the DISR0 register will clear the pending
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* interrupt.
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*/
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eif &= ~bit;
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putreg32((1 << i), S32K3XX_SIUL2_DISR0);
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}
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}
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return OK;
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}
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#endif /* CONFIG_S32K3XX_EIRQINTS */
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/****************************************************************************
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* Name: s32k3xx_wkpuinterrupt
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*
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* Description:
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* Wakeup Unit (WKPU) interrupt handling.
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*
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****************************************************************************/
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#ifdef CONFIG_S32K3XX_WKPUINTS
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static int s32k3xx_wkpuinterrupt(int irq, void *context, void *arg)
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{
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uint32_t wisr;
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uint32_t irer;
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uint32_t wisr_64;
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uint32_t irer_64;
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uint64_t eif;
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int i;
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/* Find interrupt flags for all enabled interrupts */
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wisr = getreg32(S32K3XX_WKPU_WISR);
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irer = getreg32(S32K3XX_WKPU_IRER);
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wisr_64 = getreg32(S32K3XX_WKPU_WISR_64);
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irer_64 = getreg32(S32K3XX_WKPU_IRER_64);
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eif = (wisr & irer) | (((uint64_t) (wisr_64 & irer_64)) << 32);
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/* Examine each WKPU source */
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for (i = WKPU_SRC_OFFSET; (i < 64) && (eif != 0); i++)
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{
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uint64_t bit = (1ULL << i);
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if ((eif & bit) != 0)
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{
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unsigned int index = i - WKPU_SRC_OFFSET; /* g_wkpuisrs only contains IRQ handlers for external WKPU sources */
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if (g_wkpuisrs[index].handler != NULL)
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{
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xcpt_t handler = g_wkpuisrs[index].handler;
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void *argument = g_wkpuisrs[index].arg;
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/* There is a registered interrupt handler... invoke it */
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handler(irq, context, argument);
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}
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/* Writing a one to the WISR register will clear the pending
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* interrupt.
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*/
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eif &= ~bit;
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if (i < 32)
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{
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putreg32((1 << i), S32K3XX_WKPU_WISR);
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}
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else
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{
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putreg32((1 << (i - 32)), S32K3XX_WKPU_WISR_64);
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}
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}
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}
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return OK;
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}
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#endif /* CONFIG_S32K3XX_WKPUINTS */
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: s32k3xx_pinirq_initialize
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*
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* Description:
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* Initialize logic to support a second level of interrupt decoding for
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* GPIO pins.
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*
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****************************************************************************/
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void s32k3xx_pinirq_initialize(void)
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{
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#ifdef CONFIG_S32K3XX_EIRQINTS
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irq_attach(S32K3XX_IRQ_SIUL2_VEC0, s32k3xx_eirqinterrupt, NULL);
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putreg8(0xff, S32K3XX_SIUL2_DISR0_IRQ0);
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up_enable_irq(S32K3XX_IRQ_SIUL2_VEC0);
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irq_attach(S32K3XX_IRQ_SIUL2_VEC1, s32k3xx_eirqinterrupt, NULL);
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putreg8(0xff, S32K3XX_SIUL2_DISR0_IRQ1);
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up_enable_irq(S32K3XX_IRQ_SIUL2_VEC1);
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irq_attach(S32K3XX_IRQ_SIUL2_VEC2, s32k3xx_eirqinterrupt, NULL);
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putreg8(0xff, S32K3XX_SIUL2_DISR0_IRQ2);
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up_enable_irq(S32K3XX_IRQ_SIUL2_VEC2);
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irq_attach(S32K3XX_IRQ_SIUL2_VEC3, s32k3xx_eirqinterrupt, NULL);
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putreg8(0xff, S32K3XX_SIUL2_DISR0_IRQ3);
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up_enable_irq(S32K3XX_IRQ_SIUL2_VEC3);
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#endif /* CONFIG_S32K3XX_EIRQINTS */
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#ifdef CONFIG_S32K3XX_WKPUINTS
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irq_attach(S32K3XX_IRQ_WKPU, s32k3xx_wkpuinterrupt, NULL);
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putreg32(0xffffffff, S32K3XX_WKPU_WISR);
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putreg32(0xffffffff, S32K3XX_WKPU_WISR_64);
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up_enable_irq(S32K3XX_IRQ_WKPU);
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#endif /* CONFIG_S32K3XX_WKPUINTS */
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}
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/****************************************************************************
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* Name: s32k3xx_pinirqattach
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*
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* Description:
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* Attach a pin interrupt handler. The normal initialization sequence is:
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*
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* 1. Call s32k3xx_pinconfig() to configure the interrupting pin (pin
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* interrupts will be disabled).
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* 2. Call s32k3xx_pinirqattach() to attach the pin interrupt handling
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* function.
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* 3. Call s32k3xx_pinirqenable() to enable interrupts on the pin.
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*
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* Input Parameters:
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* pinset - Pin configuration
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* pinisr - Pin interrupt service routine
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* arg - An argument that will be provided to the interrupt service
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* routine.
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*
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* Returned Value:
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* Zero (OK) is returned on success; a negated errno value is returned on
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* any failure to indicate the nature of the failure.
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*
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****************************************************************************/
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int s32k3xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg)
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{
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unsigned int index;
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irqstate_t flags;
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#ifdef CONFIG_S32K3XX_EIRQINTS
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unsigned int imcr = (pinset & _IMCR_MASK) >> _IMCR_SHIFT;
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if (((pinset & _PIN_INPUT_MODE_MASK) != PIN_INPUT_MODE_WKPU) && \
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(imcr >= (EIRQ_IMCR_FIRST - 512)) && (imcr <= (EIRQ_IMCR_LAST - 512)))
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{
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/* Calculate the EIRQ index from the IMCR number */
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index = imcr - (EIRQ_IMCR_FIRST - 512);
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/* Attach the interrupt handler */
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flags = enter_critical_section();
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g_eirqisrs[index].handler = pinisr;
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g_eirqisrs[index].arg = arg;
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leave_critical_section(flags);
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return OK;
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}
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#endif /* CONFIG_S32K3XX_EIRQINTS */
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#ifdef CONFIG_S32K3XX_WKPUINTS
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if ((pinset & _PIN_INPUT_MODE_MASK) == PIN_INPUT_MODE_WKPU)
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{
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/* Get the WPKU index based on pinset */
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index = (pinset & _WKPU_MASK) >> _WKPU_SHIFT; /* Don't add offset */
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/* Attach the interrupt handler */
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flags = enter_critical_section();
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g_wkpuisrs[index].handler = pinisr;
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g_wkpuisrs[index].arg = arg;
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leave_critical_section(flags);
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return OK;
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}
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#endif /* CONFIG_S32K3XX_WKPUINTS */
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return -EINVAL;
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}
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/****************************************************************************
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* Name: s32k3xx_pinirqenable
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*
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* Description:
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* Enable the interrupt for specified pin IRQ
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*
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****************************************************************************/
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void s32k3xx_pinirqenable(uint32_t pinset)
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{
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unsigned int index;
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#ifdef CONFIG_S32K3XX_EIRQINTS
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unsigned int imcr = (pinset & _IMCR_MASK) >> _IMCR_SHIFT;
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if (((pinset & _PIN_INPUT_MODE_MASK) != PIN_INPUT_MODE_WKPU) && \
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(imcr >= (EIRQ_IMCR_FIRST - 512)) && (imcr <= (EIRQ_IMCR_LAST - 512)))
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{
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index = imcr - (EIRQ_IMCR_FIRST - 512);
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switch (pinset & _PIN_INT_MASK)
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{
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case PIN_INT_RISING:
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{
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modifyreg32(S32K3XX_SIUL2_IREER0, 0, 1 << index); /* Enable rising-edge triggered events */
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modifyreg32(S32K3XX_SIUL2_IFEER0, 1 << index, 0); /* Disable falling-edge triggered events */
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}
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break;
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case PIN_INT_FALLING:
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{
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modifyreg32(S32K3XX_SIUL2_IREER0, 0, 1 << index); /* Enable falling-edge triggered events */
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modifyreg32(S32K3XX_SIUL2_IFEER0, 1 << index, 0); /* Disable rising-edge triggered events */
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}
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break;
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case PIN_INT_BOTH:
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{
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modifyreg32(S32K3XX_SIUL2_IREER0, 0, 1 << index); /* Enable rising-edge triggered events */
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modifyreg32(S32K3XX_SIUL2_IFEER0, 0, 1 << index); /* Enable falling-edge triggered events */
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}
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break;
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default:
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break;
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}
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/* Enable interrupt requests */
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modifyreg32(S32K3XX_SIUL2_DIRER0, 0, 1 << index);
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}
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#endif /* CONFIG_S32K3XX_EIRQINTS */
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#ifdef CONFIG_S32K3XX_WKPUINTS
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if ((pinset & _PIN_INPUT_MODE_MASK) == PIN_INPUT_MODE_WKPU)
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{
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/* Get the WPKU index based on pinset */
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index = ((pinset & _WKPU_MASK) >> _WKPU_SHIFT) + WKPU_SRC_OFFSET;
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if (index < 32)
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{
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switch (pinset & _PIN_INT_MASK)
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{
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case PIN_INT_RISING:
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{
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modifyreg32(S32K3XX_WKPU_WIREER, 0, 1 << index); /* Enable rising-edge triggered events */
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modifyreg32(S32K3XX_WKPU_WIFEER, 1 << index, 0); /* Disable falling-edge triggered events */
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}
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break;
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case PIN_INT_FALLING:
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{
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modifyreg32(S32K3XX_WKPU_WIFEER, 0, 1 << index); /* Enable falling-edge triggered events */
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modifyreg32(S32K3XX_WKPU_WIREER, 1 << index, 0); /* Disable rising-edge triggered events */
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}
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break;
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case PIN_INT_BOTH:
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{
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modifyreg32(S32K3XX_WKPU_WIREER, 0, 1 << index); /* Enable rising-edge triggered events */
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modifyreg32(S32K3XX_WKPU_WIFEER, 0, 1 << index); /* Enable falling-edge triggered events */
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}
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break;
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default:
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break;
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}
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/* Enable analog glitch filter */
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modifyreg32(S32K3XX_WKPU_WIFER, 0, 1 << index);
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/* Enable interrupt requests */
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modifyreg32(S32K3XX_WKPU_IRER, 0, 1 << index);
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}
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else
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{
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switch (pinset & _PIN_INT_MASK)
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{
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case PIN_INT_RISING:
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{
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modifyreg32(S32K3XX_WKPU_WIREER_64, 0, 1 << (index - 32)); /* Enable rising-edge triggered events */
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modifyreg32(S32K3XX_WKPU_WIFEER_64, 1 << (index - 32), 0); /* Disable falling-edge triggered events */
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}
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break;
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case PIN_INT_FALLING:
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{
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modifyreg32(S32K3XX_WKPU_WIFEER_64, 0, 1 << (index - 32)); /* Enable falling-edge triggered events */
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modifyreg32(S32K3XX_WKPU_WIREER_64, 1 << (index - 32), 0); /* Disable rising-edge triggered events */
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}
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break;
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case PIN_INT_BOTH:
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{
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modifyreg32(S32K3XX_WKPU_WIREER_64, 0, 1 << (index - 32)); /* Enable rising-edge triggered events */
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modifyreg32(S32K3XX_WKPU_WIFEER_64, 0, 1 << (index - 32)); /* Enable falling-edge triggered events */
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}
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break;
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default:
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break;
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}
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/* Enable analog glitch filter */
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modifyreg32(S32K3XX_WKPU_WIFER_64, 0, 1 << (index - 32));
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/* Enable interrupt requests */
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modifyreg32(S32K3XX_WKPU_IRER_64, 0, 1 << (index - 32));
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}
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}
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#endif /* CONFIG_S32K3XX_WKPUINTS */
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}
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/****************************************************************************
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* Name: s32k3xx_pinirqdisable
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*
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* Description:
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* Disable the interrupt for specified pin
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*
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****************************************************************************/
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void s32k3xx_pinirqdisable(uint32_t pinset)
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{
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unsigned int index;
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#ifdef CONFIG_S32K3XX_EIRQINTS
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unsigned int imcr = (pinset & _IMCR_MASK) >> _IMCR_SHIFT;
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if (((pinset & _PIN_INPUT_MODE_MASK) != PIN_INPUT_MODE_WKPU) && \
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(imcr >= (EIRQ_IMCR_FIRST - 512)) && (imcr <= (EIRQ_IMCR_LAST - 512)))
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{
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index = imcr - (EIRQ_IMCR_FIRST - 512);
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modifyreg32(S32K3XX_SIUL2_DIRER0, 1 << index, 0); /* Disable interrupt requests */
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modifyreg32(S32K3XX_SIUL2_IREER0, 1 << index, 0); /* Disable rising-edge triggered events */
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modifyreg32(S32K3XX_SIUL2_IFEER0, 1 << index, 0); /* Disable falling-edge triggered events */
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}
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#endif /* CONFIG_S32K3XX_EIRQINTS */
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#ifdef CONFIG_S32K3XX_WKPUINTS
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if ((pinset & _PIN_INPUT_MODE_MASK) == PIN_INPUT_MODE_WKPU)
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{
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/* Get the WPKU index based on pinset */
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index = ((pinset & _WKPU_MASK) >> _WKPU_SHIFT) + WKPU_SRC_OFFSET;
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if (index < 32)
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{
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modifyreg32(S32K3XX_WKPU_IRER, 1 << index, 0); /* Disable interrupt requests */
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modifyreg32(S32K3XX_WKPU_WIREER, 1 << index, 0); /* Disable rising-edge triggered events */
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modifyreg32(S32K3XX_WKPU_WIFEER, 1 << index, 0); /* Disable falling-edge triggered events */
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modifyreg32(S32K3XX_WKPU_WIFER, 1 << index, 0); /* Disable analog glitch filter */
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}
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else
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{
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modifyreg32(S32K3XX_WKPU_IRER_64, 1 << (index - 32), 0); /* Disable interrupt requests */
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modifyreg32(S32K3XX_WKPU_WIREER_64, 1 << (index - 32), 0); /* Disable rising-edge triggered events */
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modifyreg32(S32K3XX_WKPU_WIFEER_64, 1 << (index - 32), 0); /* Disable falling-edge triggered events */
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modifyreg32(S32K3XX_WKPU_WIFER_64, 1 << (index - 32), 0); /* Disable analog glitch filter */
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}
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}
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#endif /* CONFIG_S32K3XX_WKPUINTS */
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}
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#endif /* CONFIG_S32K3XX_GPIOIRQ */
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