We need to add a delay between setting and clearing the endpoint reset
bit in SAM_UDP_RSTEP. Without the delay the USB controller will (may?)
not reset the endpoint.
If the endpoint is not being reset, the Data Toggle (DTGLE) bit will
not to be cleared which will cause the next transaction to fail if
DTGLE is 1. If that happens the host will time-out and reset the bus.
Adding this delay may also fix the USBMSC_STALL_RACEWAR in
usbmsc_scsi.c, however this has not been verified yet.
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