486 lines
16 KiB
ArmAsm
486 lines
16 KiB
ArmAsm
/****************************************************************************
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* arch/xtensa/src/common/xtensa_user_handler.S
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*
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* Adapted from use in NuttX by:
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Derives from logic originally provided by Cadence Design Systems Inc.
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*
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* Copyright (c) 2006-2015 Cadence Design Systems Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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****************************************************************************/
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.file "xtensa_user_handler.S"
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/* NOTES on the use of 'call0' for long jumps instead of 'j':
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*
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* 1. This file should be assembled with the -mlongcalls option to xt-xcc.
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*
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* 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
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* a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the
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* distance from the call to the destination. The linker then relaxes
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* it back to 'call0 dest' if it determines that dest is within range.
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* This allows more flexibility in locating code without the performance
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* overhead of the 'l32r' literal data load in cases where the destination
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* is in range of 'call0'. There is an additional benefit in that 'call0'
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* has a longer range than 'j' due to the target being word-aligned, so
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* the 'l32r' sequence is less likely needed.
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*
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* 3. The use of 'call0' with -mlongcalls requires that register a0 not be
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* live at the time of the call, which is always the case for a function
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* call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.
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*
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* 4. This use of 'call0' is independent of the C function call ABI.
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*/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include <arch/xtensa/core.h>
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#include <arch/xtensa/xtensa_specregs.h>
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#include "chip_macros.h"
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/****************************************************************************
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* Assembly Language Macros
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****************************************************************************/
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/****************************************************************************
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* Macro: ps_setup
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*
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* Description:
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* Set up PS for C, enable interrupts above this level and clear EXCM.
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*
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* Entry Conditions:
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* level - interrupt level
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* tmp - scratch register
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*
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* Side Effects:
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* PS and scratch register modified
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*
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* Assumptions:
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* - PS.EXCM = 1, C calling disabled
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*
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****************************************************************************/
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.macro ps_setup level tmp
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#if 0 /* Nested interrupts no yet supported */
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# ifdef __XTENSA_CALL0_ABI__
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/* Disable interrupts at level and below */
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movi \tmp, PS_INTLEVEL(\level) | PS_UM
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# else
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movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE
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# endif
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#else
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# ifdef __XTENSA_CALL0_ABI__
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/* Disable all low- and medium-priority interrupts. Nested are not yet
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* supported.
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*/
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movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
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# else
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movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
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# endif
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#endif
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wsr \tmp, PS
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rsync
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.endm
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/****************************************************************************
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* Waypoints
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****************************************************************************/
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/* Insert some waypoints for jumping beyond the signed 8-bit range of
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* conditional branch instructions, so the conditional branchces to specific
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* exception handlers are not taken in the mainline. Saves some cycles in the
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* mainline.
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*/
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.section HANDLER_SECTION, "ax"
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.align 4
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_xtensa_to_level1_handler:
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call0 _xtensa_level1_handler /* Jump to level1 interrupt handler */
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#if XCHAL_HAVE_WINDOWED
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.align 4
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_xtensa_to_alloca_handler:
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call0 _xtensa_alloca_handler /* Jump to window vectors section */
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#endif
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.align 4
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_xtensa_to_syscall_handler:
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call0 _xtensa_syscall_handler /* Jump to syscall exception handler */
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#ifdef CONFIG_XTENSA_CP_LAZY
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#if XCHAL_CP_NUM > 0
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.align 4
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_xtensa_to_coproc_handler:
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call0 _xtensa_coproc_handler /* Jump to copressor exception handler */
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#endif
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#endif /* CONFIG_XTENSA_CP_LAZY */
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/****************************************************************************
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* Name: _xtensa_user_handler
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*
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* Description:
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* User exception handler.
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*
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* Entry Conditions:
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* A0 saved in EXCSAVE_1. All other register as upon exception.
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*
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****************************************************************************/
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.type _xtensa_user_handler, @function
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.global _xtensa_user_handler
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.align 4
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_xtensa_user_handler:
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/* If level 1 interrupt then jump to the dispatcher */
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rsr a0, EXCCAUSE
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beqi a0, EXCCAUSE_LEVEL1INTERRUPT, _xtensa_to_level1_handler
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#ifdef CONFIG_XTENSA_CP_LAZY
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#if XCHAL_CP_NUM > 0
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/* Handle any coprocessor exceptions. Rely on the fact that exception
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* numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors.
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*/
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bgeui a0, EXCCAUSE_CP0_DISABLED, _xtensa_to_coproc_handler
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#endif
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#endif /* CONFIG_XTENSA_CP_LAZY */
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/* Handle alloca and syscall exceptions */
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#if XCHAL_HAVE_WINDOWED
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beqi a0, EXCCAUSE_ALLOCA, _xtensa_to_alloca_handler
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#endif
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beqi a0, EXCCAUSE_SYSCALL, _xtensa_to_syscall_handler
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/* Handle all other exceptions. All can have user-defined handlers. */
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/* NOTE: we'll stay on the user stack for exception handling. */
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/* Allocate exception frame and save minimal context. */
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mov a0, sp /* sp == a1 */
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addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */
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s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */
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rsr a0, EPS /* Save interruptee's PS */
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s32i a0, sp, (4 * REG_PS)
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rsr a0, EPC_1 /* Save interruptee's PC */
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s32i a0, sp, (4 * REG_PC)
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rsr a0, EXCSAVE_1 /* Save interruptee's a0 */
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s32i a0, sp, (4 * REG_A0)
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/* Save rest of interrupt context. */
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s32i a2, sp, (4 * REG_A2)
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mov a2, sp /* Address of state save on stack */
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call0 _xtensa_context_save /* Save full register state */
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/* Save exc cause and vaddr into exception frame */
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rsr a0, EXCCAUSE
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s32i a0, sp, (4 * REG_EXCCAUSE)
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rsr a0, EXCVADDR
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s32i a0, sp, (4 * REG_EXCVADDR)
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/* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
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#ifdef __XTENSA_CALL0_ABI__
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movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
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#else
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movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
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#endif
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wsr a0, PS
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/* Call xtensa_user, passing both the EXCCAUSE and a pointer to the
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* beginning of the register save area.
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*/
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#ifdef __XTENSA_CALL0_ABI__
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rsr a2, EXCCAUSE /* Argument 1 (a2) = EXCCAUSE */
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mov a3, sp /* Argument 2 (a2) = pointer to register save area */
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calx0 xtensa_user /* Call xtensa_user */
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#else
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rsr a6, EXCCAUSE /* Argument 1 (a2) = EXCCAUSE */
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mov a7, sp /* Argument 2 (a2) = pointer to register save area */
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call4 xtensa_user /* Call xtensa_user */
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#endif
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/* xtensa_user should not return */
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1: j 1b
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/****************************************************************************
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* Name: _xtensa_syscall_handler
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*
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* Description:
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* Syscall Exception Handler (jumped to from User Exception Handler).
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* Syscall 0 is required to spill the register windows (no-op in Call 0 ABI).
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* Only syscall 0 is handled here. Other syscalls return -1 to caller in a2.
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*
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* Entry Conditions:
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* A0 saved in EXCSAVE_1. All other register as upon exception.
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*
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****************************************************************************/
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.section HANDLER_SECTION, "ax"
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.type _xtensa_syscall_handler, @function
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.align 4
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_xtensa_syscall_handler:
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/* Allocate stack frame and save A0, A1, and PS */
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mov a0, sp /* sp == a1 */
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addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */
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s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */
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rsr a0, EPS /* Save interruptee's PS */
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s32i a0, sp, (4 * REG_PS)
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rsr a0, EXCSAVE_1 /* Save interruptee's a0 */
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s32i a0, sp, (4 * REG_A0)
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/* Save EPC */
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#ifdef XCHAL_HAVE_LOOPS
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/* Save A2 and A3 now to give us some registers to work with. A0, A2
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* and A3 are now available. NOTE that A3 will get saved again in
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* _xtensa_context_save().
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*/
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s32i a2, sp, (4 * REG_A2) /* Save interruptee's A2 */
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s32i a2, sp, (4 * REG_A2) /* Save interruptee's A2 */
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/* Get the interruptee's PC and skip over the 'syscall' instruction.
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* If it's at the end of a zero-overhead loop and it's not on the last
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* iteration, decrement loop counter and skip to beginning of loop.
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*/
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rsr a2, EPC_1 /* a2 = PC of 'syscall' */
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addi a3, a2, 3 /* Increment PC */
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rsr a0, LEND /* Skip if PC != LEND */
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bne a3, a0, 1f
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rsr a0, LCOUNT /* Skip if LCOUNT == 0 */
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beqz a0, 1f
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addi a0, a0, -1 /* Decrement LCOUNT */
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rsr a3, LBEG /* Set PC = LBEG */
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wsr a0, LCOUNT /* Save the new LCOUNT */
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1:
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wsr a3, EPC_1 /* Update PC */
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s32i a3, sp, (4 * REG_PC)
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#else
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/* Get the interruptee's PC and skip over the 'syscall' instruction. */
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rsr a1, EPC_1 /* a2 = PC of 'syscall' */
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addi a0, a1, 3 /* ++PC */
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wsr a0, EPC_1 /* Update PC */
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s32i a0, sp, (4 * REG_PC)
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/* Save a2 which will hold the argument to _xtensa_context_save*/
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s32i a2, sp, (4 * REG_A2) /* Save interruptee's A2 */
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#endif
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/* Save rest of interrupt context. */
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mov a2, sp /* Address of state save on stack */
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call0 _xtensa_context_save /* Save full register state */
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/* Set up PS for C, enable interrupts above this level and clear EXCM. */
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ps_setup 1 a0
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/* Dispatch the sycall as with other interrupts. */
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mov a12, sp /* a12 = address of register save area */
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#ifdef __XTENSA_CALL0_ABI__
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movi a2, XTENSA_IRQ_SYSCALL /* Argument 1: IRQ number */
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mov a3, sp /* Argument 2: Top of stack = register save area */
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call0 xtensa_irq_dispatch /* Call xtensa_int_decode */
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/* On return from xtensa_irq_dispatch, a2 will contain the address of the new
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* register save area. Usually this would be the same as the current SP.
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* But in the event of a context switch, A2 will instead refer to the TCB
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* register save area.
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*/
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#else
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movi a6, XTENSA_IRQ_SYSCALL /* Argument 1: IRQ number */
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mov a7, sp /* Argument 2: Top of stack = register save area */
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call4 xtensa_irq_dispatch /* Call xtensa_int_decode */
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/* On return from xtensa_irq_dispatch, a5 will contain the address of the new
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* register save area. Usually this would be the same as the current SP.
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* But in the event of a context switch, A2 will instead refer to the TCB
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* register save area.
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*/
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mov a2, a6 /* Switch to the new register save area */
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#endif
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/* Restore registers in preparation to return from interrupt */
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call0 _xtensa_context_restore /* (Preserves a2) */
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/* Restore only level-specific regs (the rest were already restored) */
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l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */
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wsr a0, PS
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l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */
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wsr a0, EPC_1
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l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */
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l32i sp, a2, (4 * REG_A1) /* Remove interrupt stack frame */
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l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */
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rsync /* Ensure EPS and EPC written */
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/* Return from exception. RFE returns from either the UserExceptionVector
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* or the KernelExceptionVector. RFE sets PS.EXCM back to 0, and then
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* jumps to the address in EPC[1]. PS.UM and PS.WOE are left unchanged.
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*/
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rfe
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/****************************************************************************
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* Name: _xtensa_coproc_handler
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*
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* Description:
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* Co-Processor Exception Handler (jumped to from User Exception Handler).
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* This logic handlers handles the User Coprocessor[n]Disabled exceptions,
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* n=0-7. A User Coprocessor[n]Disabled exception occurs when if logic
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* executes a co-processor n instruction while coprocessor n is disabled.
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*
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* This exception allows for lazy context switch of co-processor state:
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* CPENABLE can be cleared on each context switch. When logic on the
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* thread next accesses the co-processor, this exception will occur and
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* the exception handler may then enable the co-processor on behalf of
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* the thread.
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*
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* NuttX does not currently implement this lazy co-process enable. Rather,
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* NuttX follows the model:
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*
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* 1. A set of co-processors may be enable when each thread starts as
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* determined by CONFIG_XTENSA_CP_INITSET.
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* 2. Additional co-processors may be enabled for the thread by explicitly
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* setting the CPENABLE register when the thread starts.
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* 3. Co-processor state, including CPENABLE, is saved an restored on each
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* context switch.
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* 4. Any Coprocessor[n]Disabled exceptions result in a system PANIC.
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*
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* These exceptions are generated by co-processor instructions, which are
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* only allowed in thread code (not in interrupts or kernel code). This
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* restriction is deliberately imposed to reduce the burden of state-save/
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* restore in interrupts.
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*
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* Entry Conditions:
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* A0 saved in EXCSAVE_1. All other register as upon exception.
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*
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****************************************************************************/
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#ifdef CONFIG_XTENSA_CP_LAZY
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/* Lazy co-processor restoration is not implemented. Below, the logic simply
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* calls xtensa_user() which will crash the system with an unhandled error
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* Duplicates logic above.
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*/
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#error Lazy co-processor restoration is not implemented
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#if XCHAL_CP_NUM > 0
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.type _xtensa_coproc_handler, @function
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.align 4
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_xtensa_coproc_handler:
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/* For now, just panic */
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mov a0, sp /* sp == a1 */
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addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */
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s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */
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rsr a0, EPS /* Save interruptee's PS */
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s32i a0, sp, (4 * REG_PS)
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rsr a0, EPC_1 /* Save interruptee's PC */
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s32i a0, sp, (4 * REG_PC)
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rsr a0, EXCSAVE_1 /* Save interruptee's a0 */
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s32i a0, sp, (4 * REG_A0)
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/* Save rest of interrupt context. */
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s32i a2, sp, (4 * REG_A2)
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mov a2, sp /* Address of state save on stack */
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call0 _xtensa_context_save /* Save full register state */
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/* Save exc cause and vaddr into exception frame */
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rsr a0, EXCCAUSE
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s32i a0, sp, (4 * REG_EXCCAUSE)
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rsr a0, EXCVADDR
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s32i a0, sp, (4 * REG_EXCVADDR)
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/* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
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#ifdef __XTENSA_CALL0_ABI__
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movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
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#else
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movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
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#endif
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wsr a0, PS
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/* Call xtensa_user, passing both the EXCCAUSE and a pointer to the
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* beginning of the register save area.
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*/
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#ifdef __XTENSA_CALL0_ABI__
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rsr a2, EXCCAUSE /* Argument 1 (a2) = EXCCAUSE */
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mov a3, sp /* Argument 2 (a2) = pointer to register save area */
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calx0 xtensa_user /* Call xtensa_user */
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#else
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rsr a6, EXCCAUSE /* Argument 1 (a2) = EXCCAUSE */
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mov a7, sp /* Argument 2 (a2) = pointer to register save area */
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call4 xtensa_user /* Call xtensa_user */
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#endif
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/* xtensa_user should not return */
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1: j 1b
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#endif /* XCHAL_CP_NUM */
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#endif /* CONFIG_XTENSA_CP_LAZY */
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