Jukka Laitinen c80b8fdf24 arch/risc-v/src/mpfs/mpfs_ddr.c: Add a simple prng for memory training code ...

Implement the previously empty mpfs_ddr_rand with adapted "seiran128" code
from https://github.com/andanteyk/prng-seiran

This implements a non-secure prng, which is minimal in size. The DDR training
doesn't need cryptographically secure prng, and linking in the NuttX crypto
would increase the code size significantly for bootloaders.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

2023-08-30 12:28:21 +03:00

..

include

arch/risc-v: Add support for StarFive JH7110 SoC

2023-08-03 22:55:55 -07:00

src

arch/risc-v/src/mpfs/mpfs_ddr.c: Add a simple prng for memory training code

2023-08-30 12:28:21 +03:00

Kconfig

risc-v/litex: Add system reset and access to core control registers.

2023-08-25 17:16:28 +08:00