e38b4b2103
Basically, it reserves an area of the RTC memory to preserve the
RTC timer.
Please refer to:
fa76c82a5b
This commit also removes the rtc.dummy section because C3, C6 and
H2 don't need to skip it once the region is accessed by the same
address space using the instruction and data bus.
128 lines
5.1 KiB
Plaintext
128 lines
5.1 KiB
Plaintext
/****************************************************************************
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* boards/risc-v/espressif/common/scripts/esp32c6_flat_memory.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* ESP32-C6 Linker Script Memory Layout
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*
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* This file describes the memory layout (memory blocks) as virtual
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* memory addresses.
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*
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* esp32c6_<legacy/mcuboot>_sections.ld contains output sections to link compiler
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* output into these memory blocks.
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*
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****************************************************************************/
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#include "common.ld"
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#define SRAM_IRAM_START 0x40800000
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#define SRAM_DRAM_START 0x40800000
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#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
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/* 2nd stage bootloader iram_loader_seg start address */
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#define SRAM_DRAM_END (0x4086e610 - I_D_SRAM_OFFSET)
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#define SRAM_IRAM_ORG (SRAM_IRAM_START)
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#define SRAM_DRAM_ORG (SRAM_DRAM_START)
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#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_ORG)
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/* IDRAM0_2_SEG_SIZE_DEFAULT is used when page size is 64KB */
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#define CONFIG_MMU_PAGE_SIZE 0x10000
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#define IDRAM0_2_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 8)
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#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
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MEMORY
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{
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/* Below values assume the flash cache is on, and have the blocks this
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* uses subtracted from the length of the various regions. The 'data access
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* port' dram/drom regions map to the same iram/irom regions but are
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* connected to the data port of the CPU and e.g. allow bytewise access.
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*/
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iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
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/* Flash mapped instruction data.
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*
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* The 0x20 offset is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).
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*/
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irom_seg (RX) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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* Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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* the amount of RAM available.
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*/
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dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
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/* Flash mapped constant data.
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*
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* The 0x20 offset is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).
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*/
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drom_seg (R) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
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/* RTC fast memory (executable). Persists over deep sleep. */
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lp_ram_seg (RWX) : org = 0x50000000, len = 0x4000 - RESERVE_RTC_MEM
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/* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value.
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* It reserves the amount of LP memory that we use for this memory segment.
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* This segment is intended for keeping:
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* - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
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* - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
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* The aim of this is to keep data that will not be moved around and have a fixed address.
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*/
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lp_reserved_seg (RW): org = 0x50000000 + 0x4000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
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}
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/* The lines below define location alias for .rtc.data section
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* ESP32-C6 has no distinguished LP(RTC) fast and slow memory sections,
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* instead, there is a unified LP_RAM section.
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* Thus, the following region segments are not configurable like on other targets
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*/
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REGION_ALIAS("rtc_iram_seg", lp_ram_seg);
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REGION_ALIAS("rtc_data_seg", rtc_iram_seg);
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REGION_ALIAS("rtc_slow_seg", rtc_iram_seg);
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REGION_ALIAS("rtc_data_location", rtc_iram_seg);
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REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg );
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#if CONFIG_ESPRESSIF_RUN_IRAM
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REGION_ALIAS("default_rodata_seg", dram0_0_seg);
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REGION_ALIAS("default_code_seg", iram0_0_seg);
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#else
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REGION_ALIAS("default_rodata_seg", drom_seg);
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REGION_ALIAS("default_code_seg", irom_seg);
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#endif /* CONFIG_ESPRESSIF_RUN_IRAM */
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