fb4c593e89
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make[1]: *** No rule to make target 'tms570_spi.c', needed by '.depend'. Stop.
2.
In file included from armv7-r/arm_gicv2.c:36:
armv7-r/gic.h: In function 'arm_gic_nlines':
armv7-r/mpcore.h:63:29: error: 'CHIP_MPCORE_VBASE' undeclared (first use in this function)
63 | #define MPCORE_ICD_VBASE (CHIP_MPCORE_VBASE+MPCORE_ICD_OFFSET)
| ^~~~~~~~~~~~~~~~~
Signed-off-by: chao an <anchao@xiaomi.com>
161 lines
5.0 KiB
C
161 lines
5.0 KiB
C
/****************************************************************************
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* arch/arm/src/tms570/tms570_esm.c
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Derives from the TI "Project0" sample code which has a compatible 3-
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* clause BSD license:
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*
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* Copyright (c) 2012, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX, Texas Instruments Incorporated, nor the
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* names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <arch/irq.h>
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#include "arm_internal.h"
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#include "hardware/tms570_esm.h"
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#include "tms570_esm.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: tms570_esm_initialize
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*
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* Description:
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* Initialize the ESM.
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*
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****************************************************************************/
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int tms570_esm_initialize(void)
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{
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uint32_t regval;
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/* Disable error pin channels */
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putreg32(0xffffffff, TMS570_ESM_DEPAPR1);
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putreg32(0xffffffff, TMS570_ESM_IEPCR4);
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/* Disable interrupts */
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putreg32(0xffffffff, TMS570_ESM_IECR1);
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putreg32(0xffffffff, TMS570_ESM_IECR4);
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/* Clear error status flags */
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putreg32(0xffffffff, TMS570_ESM_SR1);
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putreg32(0xffffffff, TMS570_ESM_SR2);
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putreg32(0xffffffff, TMS570_ESM_SSR2);
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putreg32(0xffffffff, TMS570_ESM_SR3);
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putreg32(0xffffffff, TMS570_ESM_SR4);
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putreg32(0xffffffff, TMS570_ESM_SR5);
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putreg32(0xffffffff, TMS570_ESM_SSR5);
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putreg32(0xffffffff, TMS570_ESM_SR6);
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/* Setup LPC preload */
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putreg32(16384 - 1, TMS570_ESM_LTCPR);
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/* Reset error pin */
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regval = getreg32(TMS570_ESM_EPSR);
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if (regval == 0)
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{
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putreg32(5, TMS570_ESM_EKR);
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}
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else
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{
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putreg32(0, TMS570_ESM_EKR);
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}
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/* Clear interrupt level. All channels set to low level interrupt. */
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putreg32(0xffffffff, TMS570_ESM_ILCR1);
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putreg32(0xffffffff, TMS570_ESM_ILCR4);
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/* Set interrupt level (Writing zero does nothing) */
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putreg32(0, TMS570_ESM_ILSR1);
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putreg32(0, TMS570_ESM_ILSR4);
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/* Enable error pin channels */
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putreg32(0, TMS570_ESM_EEPAPR1);
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putreg32(0, TMS570_ESM_IEPSR4);
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/* Enable interrupts */
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putreg32(0, TMS570_ESM_IESR1);
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putreg32(0, TMS570_ESM_IESR4);
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return OK;
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}
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/****************************************************************************
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* Name: tms570_esm_interrupt
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*
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* Description:
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* ESM interrupt handler
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*
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****************************************************************************/
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int tms570_esm_interrupt(int irq, void *context, void *arg)
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{
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/* Save the saved processor context in CURRENT_REGS where it can be
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* accessed for register dumps and possibly context switching.
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*/
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CURRENT_REGS = (uint32_t *)context;
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/* Crash -- possibly showing diagnostic debug information. */
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_err("ERROR: ESM Interrupt. PC: %08" PRIx32 "\n", CURRENT_REGS[REG_PC]);
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PANIC();
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return OK; /* To keep the compiler happy */
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}
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