458 lines
13 KiB
Plaintext
458 lines
13 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see misc/tools/kconfig-language.txt.
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#
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choice
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prompt "CPU Architecture"
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default ARCH_ARM
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config ARCH_8051
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bool "8051"
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select CUSTOM_STACK
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---help---
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Intel 8051 architectures and derivaties
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config ARCH_ARM
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bool "ARM"
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select ARCH_HAVE_INTERRUPTSTACK
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select ARCH_HAVE_VFORK
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select ARCH_HAVE_STACKCHECK
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select ARCH_HAVE_CUSTOMOPT
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---help---
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The ARM architectures
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config ARCH_AVR
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bool "AVR"
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select ARCH_NOINTC
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select ARCH_HAVE_INTERRUPTSTACK
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select ARCH_HAVE_CUSTOMOPT
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---help---
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Atmel 8-bit bit AVR and 32-bit AVR32 architectures
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config ARCH_HC
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bool "Freescale HC"
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select ARCH_NOINTC
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select ARCH_HAVE_INTERRUPTSTACK
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---help---
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Freescale HC architectures (M9S12)
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config ARCH_MIPS
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bool "MIPS"
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select ARCH_HAVE_INTERRUPTSTACK
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select ARCH_HAVE_CUSTOMOPT
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---help---
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MIPS architectures (PIC32)
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config ARCH_RGMP
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bool "RGMP"
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---help---
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RTOS and GPOS on Multi-Processor (RGMP) architecture. See
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http://rgmp.sourceforge.net/wiki/index.php/Main_Page.
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config ARCH_SH
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bool "Renesas"
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select ARCH_NOINTC
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select ARCH_HAVE_INTERRUPTSTACK
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---help---
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Renesas architectures (SH and M16C).
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config ARCH_SIM
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bool "Simulation"
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---help---
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Linux/Cywgin user-mode simulation.
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config ARCH_X86
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bool "x86"
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---help---
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Intel x86 architectures.
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config ARCH_Z16
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bool "ZNEO"
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select ARCH_HAVE_HEAP2
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---help---
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ZiLOG ZNEO 16-bit architectures (z16f).
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config ARCH_Z80
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bool "z80"
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select ARCH_HAVE_HEAP2
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---help---
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ZiLOG 8-bit architectures (z80, ez80, z8).
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endchoice
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config ARCH
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string
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default "8051" if ARCH_8051
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default "arm" if ARCH_ARM
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default "avr" if ARCH_AVR
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default "hc" if ARCH_HC
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default "mips" if ARCH_MIPS
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default "rgmp" if ARCH_RGMP
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default "sh" if ARCH_SH
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default "sim" if ARCH_SIM
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default "x86" if ARCH_X86
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default "z16" if ARCH_Z16
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default "z80" if ARCH_Z80
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source arch/8051/Kconfig
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source arch/arm/Kconfig
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source arch/avr/Kconfig
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source arch/hc/Kconfig
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source arch/mips/Kconfig
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source arch/rgmp/Kconfig
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source arch/sh/Kconfig
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source arch/sim/Kconfig
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source arch/x86/Kconfig
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source arch/z16/Kconfig
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source arch/z80/Kconfig
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comment "Architecture Options"
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config ARCH_NOINTC
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bool
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default n
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config ARCH_VECNOTIRQ
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bool
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default n
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config ARCH_DMA
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bool
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default n
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config ARCH_HAVE_IRQPRIO
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bool
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default n
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config CUSTOM_STACK
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bool
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default n
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config ADDRENV
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bool
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default n
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config ARCH_HAVE_VFORK
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bool
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default n
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config ARCH_HAVE_MMU
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bool
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default n
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config ARCH_NAND_HWECC
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bool
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default n
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config ARCH_IRQPRIO
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bool "Prioritized interrupt support"
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default n
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depends on ARCH_HAVE_IRQPRIO
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---help---
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Enable support for prioritized interrupts.
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NOTE: The use of interrupt priorities implies that you also have
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support for nested interrupts. Most architectures do not support
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nesting of interupts or, if they do, they only supported nested
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interrupts with certain configuration options. So this selection
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should be used with caution.
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config ARCH_STACKDUMP
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bool "Dump stack on assertions"
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default n
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---help---
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Enable to do stack dumps after assertions
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config ENDIAN_BIG
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bool "Big Endian Architecture"
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default n
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---help---
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Select if architecture operates using big-endian byte ordering.
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config ARCH_HAVE_RAMFUNCS
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bool
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default n
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config ARCH_RAMFUNCS
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bool "Copy functions to RAM on startup"
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default n
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depends on ARCH_HAVE_RAMFUNCS
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---help---
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Copy some functions to RAM at boot time. This is done in some
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architectures to improve performance. In other cases, it is done
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so that FLASH can be reconfigured while the MCU executes out of
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SRAM.
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config ARCH_HAVE_RAMVECTORS
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bool
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default n
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config ARCH_RAMVECTORS
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bool "Support RAM interrupt vectors"
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default n
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depends on ARCH_HAVE_RAMVECTORS
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---help---
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If ARCH_RAMVECTORS is defined, then the architecture will support
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modifiable vectors in a RAM-based vector table.
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comment "Board Settings"
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config BOARD_LOOPSPERMSEC
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int "Delay loops per millisecond"
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default 5000
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---help---
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Simple delay loops are used by some logic, especially during boot-up,
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driver initialization. These delay loops must be calibrated for each
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board in order to assure accurate timing by the delay loops.
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config ARCH_CALIBRATION
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bool "Calibrate delay loop"
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default n
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---help---
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Enables some built in instrumentation that causes a 100 second delay
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during boot-up. This 100 second delay serves no purpose other than it
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allows you to calibratre BOARD_LOOPSPERMSEC. You simply use a stop
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watch to measure the actual delay then adjust BOARD_LOOPSPERMSEC until
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the actual delay is 100 seconds.
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comment "Interrupt options"
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config ARCH_HAVE_INTERRUPTSTACK
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bool
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default n
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config ARCH_INTERRUPTSTACK
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int "Interrupt Stack Size"
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depends on ARCH_HAVE_INTERRUPTSTACK
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default 0
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---help---
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This architecture supports an interrupt stack. If defined, this symbol
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will be the size of the interrupt stack in bytes. If not defined (or
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defined to be zero), the user task stacks will be used during interrupt
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handling.
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config ARCH_HAVE_HIPRI_INTERRUPT
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bool
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default n
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config ARCH_HIPRI_INTERRUPT
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bool "High priority interrupts"
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default n
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depends on ARCH_HAVE_HIPRI_INTERRUPT && ARCH_HAVE_IRQPRIO
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select ARMV7M_USEBASEPRI
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select ARCH_IRQPRIO
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---help---
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NOTE: This description is currently unique to the Cortex-M family
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which is the only family that currently supports this feature. The
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general feature is not conceptually unique to the Cortex-M but it
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is extended to any other family, then this discussion will have to
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be generalized.
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If ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
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by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so
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that most interrupts will not have execution priority. SVCall must
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have execution priority in all cases.
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In the normal cases, interrupts are not nest-able and all interrupts
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run at an execution priority between NVIC_SYSH_PRIORITY_MIN and
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NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for
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SVCall).
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If, in addition, ARCH_HIPRI_INTERRUPT is defined, then special high
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priority interrupts are supported. These are not "nested" in the
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normal sense of the word. These high priority interrupts can
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interrupt normal processing but execute outside of OS (although they
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can "get back into the game" via a PendSV interrupt).
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How do you specify a high priority interrupt? You need to do two
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things:
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1) You need to change the address in the vector table so that
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the high priority interrupt vectors to your special C
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interrupt handler. There are two ways to do this:
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a) If you select CONFIG_ARCH_RAMVECTORS, then vectors will
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be kept in RAM and the system will support the interface:
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int up_ramvec_attach(int irq, up_vector_t vector)
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that can be used to attach your C interrupt handler to the
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vector at run time.
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b) Alternatively, you could keep your vectors in FLASH but in
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order to this, you would have to develop your own custom
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vector table.
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2) Then set the priority of your interrupt to NVIC to
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NVIC_SYSH_HIGH_PRIORITY using the standard interface:
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int up_prioritize_irq(int irq, int priority)
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NOTE: ARCH_INTERRUPTSTACK must be set in kernel mode (NUTTX_KERNEL).
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In kernel mode without an interrupt stack, the interrupt handler
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will set the MSP to the stack pointer of the interrupted thread. If
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the interrupted thread was a privileged thread, that will be the MSP
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otherwise it will be the PSP. If the PSP is used, then the value of
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the MSP will be invalid when the interrupt handler returns because
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it will be a pointer to an old position in the unprivileged stack.
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Then when the high priority interrupt occurs and uses this stale MSP,
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there will most likely be a system failure.
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If the interrupt stack is selected, on the other hand, then the
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interrupt handler will always set the the MSP to the interrupt
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stack. So when the high priority interrupt occurs, it will either
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use the MSP of the last privileged thread to run or, in the case of
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the nested interrupt, the interrupt stack if no privileged task has
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run
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config ARCH_INT_DISABLEALL
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bool "Disable high priority interrupts"
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default y
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depends on ARCH_HIPRI_INTERRUPT && EXPERIMENTAL
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---help---
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If ARCH_HIPRI_INTERRUPT is defined, then special high priority
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interrupts are supported. These are not "nested" in the normal
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sense of the word. These high priority interrupts can interrupt
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normal processing but execute outside of OS (although they can "get
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back into the game" via a PendSV interrupt).
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In the normal course of things, interrupts must occasionally be
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disabled using the irqsave() inline function to prevent contention
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in use of resources that may be shared between interrupt level and
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non-interrupt level logic. Now the question arises, if
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ARCH_HIPRI_INTERRUPT, do we disable all interrupts (except SVCall),
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or do we only disable the "normal" interrupts. Since the high
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priority interrupts cannot interact with the OS, you may want to
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permit the high priority interrupts even if interrupts are
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disabled. The setting ARCH_INT_DISABLEALL can be used to select
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either behavior:
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----------------------------+--------------+----------------------------
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CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
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----------------------------+--------------+--------------+-------------
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CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
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----------------------------+--------------+--------------+-------------
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| | | SVCall
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| SVCall | SVCall | HIGH
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Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
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| | MAXNORMAL |
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----------------------------+--------------+--------------+-------------
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NOTE: This does not work now because interrupts get disabled in the
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standard interrupt handling, prohibiting nesting. Fix is simple: Need
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to used more priority levels so that we can make a cleaner distinction
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with the standard interrupt handler.
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comment "Boot options"
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choice
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prompt "Boot Mode"
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default BOOT_RUNFROMFLASH
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config BOOT_RUNFROMEXTSRAM
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bool "Run from external SRAM"
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---help---
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Some configuration support booting and running from external SRAM.
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config BOOT_RUNFROMFLASH
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bool "Boot and run from flash"
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---help---
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Most configurations support XIP operation from FLASH but must copy
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initialized .data sections to RAM. (This is the default).
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config BOOT_RUNFROMISRAM
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bool "Boot and run from internal SRAM"
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---help---
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Some configuration support booting and running from internal SRAM.
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config BOOT_RUNFROMSDRAM
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bool "Boot and run from external SDRAM"
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---help---
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Some configuration support booting and running from external SDRAM.
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config BOOT_COPYTORAM
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bool "Boot from FLASH but copy to ram"
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---help---
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Some configurations boot in FLASH but copy themselves entirely into
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RAM for better performance.
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endchoice
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menu "Boot Memory Configuration"
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config RAM_START
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hex "Primary RAM start address (physical)"
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default 0x0
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help
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The physical start address of primary installed RAM. "Primary" RAM
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refers to the RAM that you link program code into. If program code
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does not excecute out of RAM but from FLASH, then you may designate
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any block of RAM as "primary."
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config RAM_VSTART
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hex "Primary RAM start address (virtual)"
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default 0x0
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depends on ARCH_HAVE_MMU
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help
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The virtual start address of installed primary RAM. "Primary" RAM
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refers to the RAM that you link program code into. If program code
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does not excecute out of RAM but from FLASH, then you may designate
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any block of RAM as "primary."
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config RAM_SIZE
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int "Primary RAM size"
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default 0
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help
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The size in bytes of the installed primary RAM. "Primary" RAM
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refers to the RAM that you link program code into. If program code
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does not excecute out of RAM but from FLASH, then you may designate
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any block of RAM as "primary."
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if BOOT_RUNFROMFLASH && ARCH_HAVE_MMU
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config FLASH_START
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hex "Boot FLASH start address (physical)"
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default 0x0
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help
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The physical start address of installed boot FLASH. "Boot" FLASH
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refers to the FLASH that you link program code into.
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config FLASH_VSTART
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hex "Boot FLASH start address (virtual)"
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default 0x0
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help
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The virtual start address of installed boot FLASH. "Boot" FLASH
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refers to the FLASH that you link program code into.
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config FLASH_SIZE
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int "Boot FLASH size"
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default 0
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help
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The size in bytes of the installed boot FLASH. "Boot" FLASH
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refers to the FLASH that you link program code into.
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endif # BOOT_RUNFROMFLASH && ARCH_HAVE_MMU
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config ARCH_HAVE_SDRAM
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bool
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default n
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config BOOT_SDRAM_DATA
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bool "Data in SDRAM"
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default n
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depends on ARCH_HAVE_SDRAM && !BOOT_RUNFROMSDRAM
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---help---
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This selection should be set if data lies in SDRAM (vs. SRAM) and if
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SDRAM was not previously initialized by a loader. Obviously, this
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does not apply if we booting from SDRAM because SDRAM must have been
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initialized priority to loading NuttX into SDRAM.
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In the case where SDRAM must be initialized by NuttX, the
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initialization sequence is a little different: Normally, .data and
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.bss must be initialized before starting the system. But in this
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case SDRAM must be configured by board-specific logic before the
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.data and .bss sections can be initialized.
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endmenu # Boot Memory Configuration
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