329 lines
10 KiB
C
329 lines
10 KiB
C
/****************************************************************************
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* boards/arm/sama5/sama5d2-xult/src/sam_ethernet.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/* Force verbose debug on in this file only to support unit-level testing. */
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#ifdef CONFIG_NETDEV_PHY_DEBUG
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# undef CONFIG_DEBUG_INFO
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# define CONFIG_DEBUG_INFO 1
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# undef CONFIG_DEBUG_NET
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# define CONFIG_DEBUG_NET 1
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#endif
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#include <string.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include "sam_pio.h"
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#include "sam_ethernet.h"
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#include "sama5d2-xult.h"
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#ifdef HAVE_NETWORK
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef CONFIG_SAMA5_EMACA
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# undef CONFIG_SAMA5_EMAC_ISETH0
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#endif
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#ifdef CONFIG_SAMA5_EMAC_ISETH0
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# define SAMA5_EMAC_DEVNAME "eth0"
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# define SAMA5_GMAC_DEVNAME "eth1"
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#else
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# define SAMA5_GMAC_DEVNAME "eth0"
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# define SAMA5_EMAC_DEVNAME "eth1"
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#endif
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/* Debug ********************************************************************/
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/* Extra, in-depth debug output that is only available if
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* CONFIG_NETDEV_PHY_DEBUG us defined.
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*/
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#ifdef CONFIG_NETDEV_PHY_DEBUG
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# define phyerr _err
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# define phywarn _warn
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# define phyinfo _info
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#else
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# define phyerr(x...)
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# define phywarn(x...)
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# define phyinfo(x...)
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: sam_emac_phy_enable and sam_gmac_enable
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****************************************************************************/
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#ifdef CONFIG_SAMA5_PIOE_IRQ
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#ifdef CONFIG_SAMA5_EMACA
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static void sam_emac_phy_enable(bool enable)
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{
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phyinfo("IRQ%d: enable=%d\n", IRQ_INT_ETH1, enable);
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if (enable)
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{
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sam_pioirqenable(IRQ_INT_ETH1);
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}
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else
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{
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sam_pioirqdisable(IRQ_INT_ETH1);
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}
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}
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#endif
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#ifdef CONFIG_SAMA5_GMAC
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static void sam_gmac_phy_enable(bool enable)
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{
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phyinfo("IRQ%d: enable=%d\n", IRQ_INT_ETH0, enable);
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if (enable)
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{
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sam_pioirqenable(IRQ_INT_ETH0);
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}
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else
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{
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sam_pioirqdisable(IRQ_INT_ETH0);
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}
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}
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#endif
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: sam_netinitialize
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*
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* Description:
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* Configure board resources to support networking.
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*
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****************************************************************************/
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void weak_function sam_netinitialize(void)
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{
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#ifdef CONFIG_SAMA5_EMACA
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/* Ethernet 10/100 (EMAC A) Port
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*
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* The main board contains a MICREL PHY device (KSZ8051) operating at
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* 10/100 Mbps. The board supports MII and RMII interface modes.
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*
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* The two independent PHY devices embedded on CM and MB boards are
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* connected to independent RJ-45 connectors with built-in magnetic
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* and status LEDs.
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*
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* At the De-Assertion of Reset:
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* PHY ADD[2:0]:001
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* CONFIG[2:0]:001,Mode:RMII
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* Duplex Mode:Half Duplex
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* Isolate Mode:Disable
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* Speed Mode:100Mbps
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* Nway Auto-Negotiation:Enable
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*
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* The KSZ8051 PHY interrupt is available on PE30 INT_ETH1
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*/
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phyinfo("Configuring %08x\n", PIO_INT_ETH1);
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sam_configpio(PIO_INT_ETH1);
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#endif
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#ifdef CONFIG_SAMA5_GMAC
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/* Tri-Speed Ethernet PHY
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*
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* The SAMA5D3 series-CM board is equipped with a MICREL PHY devices
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* (MICREL KSZ9021/31) operating at 10/100/1000 Mbps.
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* The board supports RGMII interface mode.
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* The Ethernet interface consists of 4 pairs of low voltage differential
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* pair signals designated from GRX and GTx plus control signals for
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* link activity indicators. These signals can be used to connect to a
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* 10/100/1000 BaseT RJ45 connector integrated on the main board.
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*
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* The KSZ9021/31 interrupt is available on PB35 INT_GETH0
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*/
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phyinfo("Configuring %08x\n", PIO_INT_ETH0);
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sam_configpio(PIO_INT_ETH0);
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#endif
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}
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/****************************************************************************
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* Name: arch_phy_irq
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*
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* Description:
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* This function may be called to register an interrupt handler that will
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* be called when a PHY interrupt occurs. This function both attaches
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* the interrupt handler and enables the interrupt if 'handler' is non-
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* NULL. If handler is NULL, then the interrupt is detached and disabled
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* instead.
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*
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* The PHY interrupt is always disabled upon return. The caller must
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* call back through the enable function point to control the state of
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* the interrupt.
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*
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* This interrupt may or may not be available on a given platform depending
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* on how the network hardware architecture is implemented. In a typical
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* case, the PHY interrupt is provided to board-level logic as a GPIO
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* interrupt (in which case this is a board-specific interface and really
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* should be called board_phy_irq()); In other cases, the PHY interrupt
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* may be cause by the chip's MAC logic (in which case arch_phy_irq()) is
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* an appropriate name. Other other boards, there may be no PHY interrupts
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* available at all. If client attachable PHY interrupts are available
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* from the board or from the chip, then CONFIG_ARCH_PHY_INTERRUPT should
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* be defined to indicate that fact.
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*
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* Typical usage:
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* a. OS service logic (not application logic*) attaches to the PHY
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* PHY interrupt and enables the PHY interrupt.
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* b. When the PHY interrupt occurs: (1) the interrupt should be
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* disabled and () work should be scheduled on the worker thread (or
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* perhaps a dedicated application thread).
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* c. That worker thread should use the SIOCGMIIPHY, SIOCGMIIREG,
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* and SIOCSMIIREG ioctl calls** to communicate with the PHY,
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* determine what network event took place (Link Up/Down?), and
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* take the appropriate actions.
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* d. It should then interact the PHY to clear any pending
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* interrupts, then re-enable the PHY interrupt.
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*
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* * This is an OS internal interface and should not be used from
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* application space. Rather applications should use the SIOCMIISIG
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* ioctl to receive a signal when a PHY event occurs.
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* ** This interrupt is really of no use if the Ethernet MAC driver
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* does not support these ioctl calls.
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*
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* Input Parameters:
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* intf - Identifies the network interface. For example "eth0". Only
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* useful on platforms that support multiple Ethernet interfaces
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* and, hence, multiple PHYs and PHY interrupts.
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* handler - The client interrupt handler to be invoked when the PHY
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* asserts an interrupt. Must reside in OS space, but can
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* signal tasks in user space. A value of NULL can be passed
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* in order to detach and disable the PHY interrupt.
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* arg - The argument that will accompany the interrupt
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* enable - A function pointer that be unused to enable or disable the
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* PHY interrupt.
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*
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* Returned Value:
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* Zero (OK) returned on success; a negated errno value is returned on
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* failure.
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*
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****************************************************************************/
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#ifdef CONFIG_SAMA5_PIOE_IRQ
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int arch_phy_irq(const char *intf, xcpt_t handler, void *arg,
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phy_enable_t *enable)
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{
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irqstate_t flags;
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pio_pinset_t pinset;
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phy_enable_t enabler;
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int irq;
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DEBUGASSERT(intf);
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ninfo("%s: handler=%p\n", intf, handler);
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#ifdef CONFIG_SAMA5_EMACA
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phyinfo("EMAC: devname=%s\n", SAMA5_EMAC_DEVNAME);
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#endif
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#ifdef CONFIG_SAMA5_GMAC
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phyinfo("GMAC: devname=%s\n", SAMA5_GMAC_DEVNAME);
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#endif
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#ifdef CONFIG_SAMA5_EMACA
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if (strcmp(intf, SAMA5_EMAC_DEVNAME) == 0)
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{
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phyinfo("Select EMAC\n");
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pinset = PIO_INT_ETH1;
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irq = IRQ_INT_ETH1;
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enabler = sam_emac_phy_enable;
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}
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else
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#endif
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#ifdef CONFIG_SAMA5_GMAC
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if (strcmp(intf, SAMA5_GMAC_DEVNAME) == 0)
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{
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phyinfo("Select GMAC\n");
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pinset = PIO_INT_ETH0;
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irq = IRQ_INT_ETH0;
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enabler = sam_gmac_phy_enable;
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}
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else
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#endif
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{
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nerr("ERROR: Unsupported interface: %s\n", intf);
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return NULL;
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}
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/* Disable interrupts until we are done. This guarantees that the
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* following operations are atomic.
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*/
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flags = enter_critical_section();
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/* Configure the interrupt */
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if (handler)
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{
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phyinfo("Configure pin: %08x\n", pinset);
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sam_pioirq(pinset);
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phyinfo("Attach IRQ%d\n", irq);
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irq_attach(irq, handler, arg);
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}
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else
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{
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phyinfo("Detach IRQ%d\n", irq);
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irq_detach(irq);
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enabler = NULL;
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}
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/* Return with the interrupt disabled in either case */
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sam_pioirqdisable(irq);
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/* Return the enabling function pointer */
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if (enable)
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{
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*enable = enabler;
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}
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/* Return the old handler (so that it can be restored) */
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leave_critical_section(flags);
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return OK;
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}
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#endif /* CONFIG_SAMA5_PIOE_IRQ */
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#endif /* HAVE_NETWORK */
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