81 lines
3.1 KiB
C
81 lines
3.1 KiB
C
/****************************************************************************
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* boards/hc/m9s12/demo9s12ne64/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_HC_M9S12_DEMO9S12NE64_INCLUDE_BOARD_H
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#define __BOARDS_HC_M9S12_DEMO9S12NE64_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* Frequency of the crystal oscillator */
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#define HCS12_OSCCLK 16000000 /* 16MHz */
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/* PLL Settings
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*
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* SYNR register controls the multiplication factor of the PLL.
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* If the PLL is on, the count in the loop divider (SYNR) register
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* effectively multiplies up the PLL clock (PLLCLK) from the reference
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* frequency by 2 x(SYNR+1).
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* PLLCLK will not be below the minimum VCO frequency (fSCM).
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*
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* The REFDV register provides a finer granularity for the PLL multiplier
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* steps.
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* The count in the reference divider divides OSCCLK frequency by REFDV + 1.
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*
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* PLLCLK = 2 * OSCCLK * (SYNR + 1) / (REFDV + 1)
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*
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* If (PLLSEL = 1), Bus Clock = PLLCLK / 2
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*/
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#define HCS12_SYNR_VALUE 0x15
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#define HCS12_REFDV_VALUE 0x15
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#define HCS12_PLLCLK (2*HCS12_OSCCLK*(HCS12_SYNR+1)/(HCS12_REFDV+1))
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#define HCS12_BUSCLK (HSC12_PLLCLK/2)
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/* LED definitions **********************************************************/
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/* The DEMO9S12NE64 board has 2 LEDs that we will encode as: */
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#define LED_STARTED 1 /* LED1 */
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#define LED_HEAPALLOCATE 1 /* LED1 */
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#define LED_IRQSENABLED 1 /* LED1 */
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#define LED_STACKCREATED 1 /* LED1 */
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#define LED_INIRQ 2 /* LED1 + LED2 */
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#define LED_SIGNAL 2 /* LED1 + LED2 */
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#define LED_ASSERTION 2 /* LED1 + LED2 */
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#define LED_PANIC 7 /* LED2 + N/C */
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/* Button definitions *******************************************************/
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#endif /* __BOARDS_HC_M9S12_DEMO9S12NE64_INCLUDE_BOARD_H */
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