415 lines
13 KiB
C
415 lines
13 KiB
C
/****************************************************************************
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* arch/arm/src/tiva/common/lm4xx_tm3c_sysctrl.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/init.h>
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#include <arch/board/board.h>
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#include "arm_internal.h"
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#include "chip.h"
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#include "tiva_sysctrl.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#if defined(LM4F) || defined(TM4C)
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# define RCC_XTALMASK (SYSCON_RCC_XTAL_MASK | SYSCON_RCC_OSCSRC_MASK | \
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SYSCON_RCC_PWRDN)
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# define RCC2_XTALMASK (SYSCON_RCC2_OSCSRC2_MASK | SYSCON_RCC2_PWRDN2 | \
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SYSCON_RCC2_DIV400 | SYSCON_RCC2_USERCC2)
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# define RCC_DIVMASK (SYSCON_RCC_SYSDIV_MASK | SYSCON_RCC_USESYSDIV | \
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SYSCON_RCC_MOSCDIS)
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# define RCC2_DIVMASK (SYSCON_RCC2_SYSDIV2LSB | SYSCON_RCC2_SYSDIV2_MASK)
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#else
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# define RCC_OSCMASK (SYSCON_RCC_IOSCDIS | SYSCON_RCC_MOSCDIS)
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# define RCC_XTALMASK (SYSCON_RCC_XTAL_MASK | SYSCON_RCC_OSCSRC_MASK | \
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SYSCON_RCC_PWRDN)
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# define RCC2_XTALMASK (SYSCON_RCC2_OSCSRC2_MASK | SYSCON_RCC2_PWRDN2 | \
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SYSCON_RCC2_SYSDIV2_MASK | SYSCON_RCC2_USERCC2)
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# define RCC_DIVMASK (SYSCON_RCC_SYSDIV_MASK | SYSCON_RCC_USESYSDIV | \
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SYSCON_RCC_IOSCDIS | SYSCON_RCC_MOSCDIS)
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# define RCC2_DIVMASK (SYSCON_RCC2_SYSDIV2_MASK)
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#endif
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#define FAST_OSCDELAY (512*1024)
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#define SLOW_OSCDELAY (4*1024)
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#define PLLLOCK_DELAY (32*1024)
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: tiva_delay
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*
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* Description:
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* Wait for the newly selected oscillator(s) to settle. This is tricky
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* because the time that we wait can be significant and is determined by
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* the previous clock setting, not the one that we are configuring.
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*
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****************************************************************************/
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static inline void tiva_delay(uint32_t delay)
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{
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__asm__ __volatile__("1:\n"
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"\tsubs %0, #1\n"
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"\tbne 1b\n"
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: "=r"(delay) : "r"(delay));
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}
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/****************************************************************************
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* Name: tiva_oscdelay
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*
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* Description:
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* Wait for the newly selected oscillator(s) to settle. This is tricky
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* because the time that we wait can be significant and is determined by
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* the previous clock setting, not the one that we are configuring.
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*
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****************************************************************************/
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static inline void tiva_oscdelay(uint32_t rcc, uint32_t rcc2)
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{
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/* Wait for the oscillator to stabilize. A smaller delay is used if the
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* current clock rate is very slow.
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*/
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uint32_t delay = FAST_OSCDELAY;
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/* Are we currently using RCC2? */
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if ((rcc2 & SYSCON_RCC2_USERCC2) != 0)
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{
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uint32_t rcc2src = rcc2 & SYSCON_RCC2_OSCSRC2_MASK;
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if ((rcc2src == SYSCON_RCC2_OSCSRC2_LFIOSC) ||
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(rcc2src == SYSCON_RCC2_OSCSRC2_32768HZ))
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{
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delay = SLOW_OSCDELAY;
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}
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}
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/* No.. using OSCSRC in RCC */
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else
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{
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uint32_t rccsrc = rcc & SYSCON_RCC_OSCSRC_MASK;
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if (rccsrc == SYSCON_RCC_OSCSRC_LFIOSC)
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{
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delay = SLOW_OSCDELAY;
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}
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}
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/* Then delay that number of loops */
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tiva_delay(delay);
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}
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/****************************************************************************
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* Name: tiva_pll_lock
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*
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* Description:
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* The new RCC values have been selected... wait for the PLL to lock on
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*
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****************************************************************************/
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static inline void tiva_pll_lock(void)
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{
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volatile uint32_t delay;
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/* Loop until the lock is achieved or until a timeout occurs */
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for (delay = PLLLOCK_DELAY; delay > 0; delay--)
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{
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/* Check if the PLL is locked on */
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if ((getreg32(TIVA_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
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{
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/* Yes.. return now */
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return;
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}
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}
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/* If we get here, then PLL lock was not achieved */
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: tiva_clock_reconfigure
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*
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* Description:
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* Called to change to new clock based on desired rcc and rcc2 settings.
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* This is use to set up the initial clocking but can be used later to
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* support slow clocked, low power consumption modes.
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*
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****************************************************************************/
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void tiva_clock_reconfigure(uint32_t newrcc, uint32_t newrcc2)
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{
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/* We are probably using the main oscillator. The main oscillator is
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* disabled on reset and so probably must be enabled here. The internal
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* oscillator is enabled on reset and if that is selected, most likely
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* nothing needs to be done.
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*/
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uint32_t rcc;
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uint32_t rcc2;
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/* Get the current values of the RCC and RCC2 registers */
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rcc = getreg32(TIVA_SYSCON_RCC);
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rcc2 = getreg32(TIVA_SYSCON_RCC2);
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#if defined(LM4F) || defined(TM4C)
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if ((rcc & SYSCON_RCC_MOSCDIS) != 0 && (newrcc & SYSCON_RCC_MOSCDIS) == 0)
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{
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uint32_t dummy;
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/* According to TM4C123GH6PM datasheet page 231 item 5.3 we must
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* perform the following steps to initialize and configure TM4C123G
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* chip to use a PLL based system clock.
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*
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* 1. Bypass the PLL and system clock divider by setting the BYPASS
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* bit and clearing the USESYS bit in the RCC register.
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*
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* 2. Select the crystal value (XTAL) and oscillator source (OSCSRC),
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* and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field
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* automatically pulls valid PLL configuration data for the
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* appropriate crystal, and clearing the PWRDN bit powers and
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* enables the PLL and its output.
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*
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* 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set
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* the USESYS bit in RCC. The SYSDIV field determines the system
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* frequency for the microcontroller.
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*
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* 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw
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* Interrupt Status (RIS) register.
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*
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* 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
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*/
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/* Step 1 - Temporarily bypass the PLL and system clock dividers */
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rcc |= SYSCON_RCC_BYPASS;
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rcc &= ~(SYSCON_RCC_USESYSDIV);
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rcc2 |= SYSCON_RCC2_BYPASS2;
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/* According to TM4C123GH6PM datasheet we must write RCC register prior
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* to writing the RCC2 register.
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*/
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putreg32(rcc, TIVA_SYSCON_RCC);
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dummy = getreg32(TIVA_SYSCON_RCC);
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UNUSED(dummy);
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putreg32(rcc2, TIVA_SYSCON_RCC2);
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/* Step 2 - Set the new crystal value, oscillator source and PLL
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* configuration.
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*/
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rcc &= ~RCC_XTALMASK;
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rcc |= (newrcc & RCC_XTALMASK);
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rcc2 &= ~RCC2_XTALMASK;
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rcc2 |= (newrcc2 & RCC2_XTALMASK);
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/* Write the new RCC/RCC2 values.
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*
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* LM4F120 Data Sheet: "Write the RCC register prior to writing the
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* RCC2 register. If a subsequent write to the RCC register is
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* required, include another register access after writing the RCC
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* register and before writing the RCC2 register."
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*/
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putreg32(rcc, TIVA_SYSCON_RCC);
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dummy = getreg32(TIVA_SYSCON_RCC);
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UNUSED(dummy);
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putreg32(rcc2, TIVA_SYSCON_RCC2);
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/* Wait for the new crystal value and oscillator source to take
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* effect
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*/
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tiva_delay(16);
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/* Step 3 - Set the requested system divider and disable the non-
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* selected oscillators.
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*/
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rcc &= ~RCC_DIVMASK;
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rcc |= (newrcc & RCC_DIVMASK);
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rcc2 &= ~RCC2_DIVMASK;
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rcc2 |= (newrcc2 & RCC2_DIVMASK);
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putreg32(rcc, TIVA_SYSCON_RCC);
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dummy = getreg32(TIVA_SYSCON_RCC);
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UNUSED(dummy);
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putreg32(rcc2, TIVA_SYSCON_RCC2);
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/* Step 4 - Will the PLL output be used to clock the system? */
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if ((newrcc & SYSCON_RCC_BYPASS) == 0)
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{
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/* Yes, wait until the PLL is locked */
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tiva_pll_lock();
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/* Step 5 - Then enable the PLL */
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rcc &= ~SYSCON_RCC_BYPASS;
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rcc2 &= ~SYSCON_RCC2_BYPASS2;
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putreg32(rcc, TIVA_SYSCON_RCC);
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dummy = getreg32(TIVA_SYSCON_RCC);
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UNUSED(dummy);
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putreg32(rcc2, TIVA_SYSCON_RCC2);
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}
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}
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#else
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if (((rcc & SYSCON_RCC_MOSCDIS) != 0 &&
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(newrcc & SYSCON_RCC_MOSCDIS) == 0) ||
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((rcc & SYSCON_RCC_IOSCDIS) != 0 &&
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(newrcc & SYSCON_RCC_IOSCDIS) == 0))
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{
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/* Temporarily bypass the PLL and system clock dividers */
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rcc |= SYSCON_RCC_BYPASS;
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rcc &= ~(SYSCON_RCC_USESYSDIV);
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putreg32(rcc, TIVA_SYSCON_RCC);
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rcc2 |= SYSCON_RCC2_BYPASS2;
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putreg32(rcc2, TIVA_SYSCON_RCC2);
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/* Enable any selected oscillators (but don't disable any yet) */
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rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK));
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putreg32(rcc, TIVA_SYSCON_RCC);
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/* Wait for the newly selected oscillator(s) to settle. This is
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* tricky because the time that we wait can be significant and is
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* determined by the previous clock setting, not the one that we are
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* configuring.
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*/
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tiva_oscdelay(rcc, rcc2);
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/* Set the new crystal value, oscillator source and PLL configuration */
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rcc &= ~RCC_XTALMASK;
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rcc |= (newrcc & RCC_XTALMASK);
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rcc2 &= ~RCC2_XTALMASK;
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rcc2 |= (newrcc2 & RCC2_XTALMASK);
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/* Clear the PLL lock interrupt */
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putreg32(SYSCON_MISC_PLLLMIS, TIVA_SYSCON_MISC);
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/* Write the new RCC/RCC2 values.
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*
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* Original LM3S Logic: Order depends upon whether RCC2 or RCC is
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* currently enabled.
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*/
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putreg32(rcc, TIVA_SYSCON_RCC);
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putreg32(rcc2, TIVA_SYSCON_RCC2);
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/* Wait for the new crystal value and oscillator source to take
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* effect
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*/
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tiva_delay(16);
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/* Set the requested system divider and disable the non-selected
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* osciallators
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*/
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rcc &= ~RCC_DIVMASK;
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rcc |= (newrcc & RCC_DIVMASK);
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rcc2 &= ~RCC2_DIVMASK;
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rcc2 |= (newrcc2 & RCC2_DIVMASK);
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/* Will the PLL output be used to clock the system? */
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if ((newrcc & SYSCON_RCC_BYPASS) == 0)
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{
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/* Yes, wait until the PLL is locked */
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tiva_pll_lock();
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/* Then enable the PLL */
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rcc &= ~SYSCON_RCC_BYPASS;
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rcc2 &= ~SYSCON_RCC2_BYPASS2;
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}
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/* Now we can set the final RCC/RCC2 values */
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putreg32(rcc, TIVA_SYSCON_RCC);
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putreg32(rcc2, TIVA_SYSCON_RCC2);
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/* Wait for the system divider to be effective */
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tiva_delay(6);
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}
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#endif
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}
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/****************************************************************************
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* Name: tiva_clock_configure
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*
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* Description:
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* Called early in the boot sequence (before .data and .bss are available)
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* in order to configure initial clocking.
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*
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****************************************************************************/
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void tiva_clock_configure(void)
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{
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#ifdef CONFIG_LM_REVA2
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/* Some early LM3 silicon returned an increase LDO voltage to 2.75V to work
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* around a PLL bug
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*/
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putreg32(SYSCON_LPDOPCTL_2750MV, TIVA_SYSCON_LDOPCTL);
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#endif
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/* Set the clocking to run with the default settings provided in the
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* board.h header file
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*/
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tiva_clock_reconfigure(TIVA_RCC_VALUE, TIVA_RCC2_VALUE);
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}
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