nuttx/boards/arm/phy62xx/phy6222
Xiang Xiao cd001725b7 arch/arm: Remove FAR and CODE from board folder(1)
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-03 16:50:52 +03:00
..
configs add phyplus_rel_1.4 2022-02-15 10:21:10 +08:00
include include: fix double include pre-processor guards 2022-01-16 11:11:14 -03:00
scripts boards: Move -fno-strict-aliasing from Make.defs to Toolchain.defs 2022-05-01 11:36:41 +03:00
src arch/arm: Remove FAR and CODE from board folder(1) 2022-05-03 16:50:52 +03:00
Kconfig phyplus first submit 2021-12-07 01:37:29 -06:00
README.txt phyplus first submit 2021-12-07 01:37:29 -06:00

STATUS
======

05/17: The basic NSH configuration is functional and shows that there is
       3-4KB of free heap space.  However, attempts to extend this have
       failed.  I suspect that 8KB of SRAM is insufficient to do much
       with the existing NSH configuration.  Perhaps some fine tuning
       can improve this situation but at this point, I think this board
       is only useful for the initial STM32 F0 bring-up, perhaps for
       embedded solutions that do not use NSH and for general
       experimentation.

       There is also support for the Nucleo boards with the STM32 F072
       and F092 MCUs.  Those ports do not suffer from these problems and
       seem to work well in fairly complex configurations.  Apparently 8KB
       is SRAM is not usable but the parts with larger 16KB and 32KB SRAMs
       are better matches.